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datasheet r01ds0261ej0110 rev.1.10 page 1 of 177 oct 30, 2015 rx230 group, rx231 group renesas mcus features 32-bit rxv2 cpu core ? max. operating frequency: 54 mhz capable of 88.56 dmips in operation at 54 mhz ? enhanced dsp: 32-bit multiply-accumulate and 16-bit multiply-subtract instructions supported ? built-in fpu: 32-bit single-precision floating point (compliant to ieee754) ? divider (fastest instruction execution takes two cpu clock cycles) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instructions, ultra-compact code ? on-chip debugging circuit ? memory protection unit (mpu) supported low power design and architecture ? operation from a single 1.8-v to 5.5-v supply ? rtc capable of operating on the battery backup power supply ? three low power consumption modes ? low power timer (lpt) that operates during the software standby state on-chip flash memory for code ? 128- to 512-kbyte capacities ? on-board or off-board user programming ? programmable at 1.8 v ? for instructions and operands on-chip data flash memory ? 8 kbytes (1,000,000 program/erase cycles (typ.)) ? bgo (background operation) on-chip sram, no wait states ? 32- to 64-kbyte size capacities data transfer functions ? dmac: incorporates four channels ? dtc: four transfer modes elc ? module operation can be initiated by event signals without using interrupts. ? linked operation between modules is possible while the cpu is sleeping. reset and supply management ? eight types of reset, including the power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? main clock oscillator frequency: 1 to 20 mhz ? external clock input frequency: up to 20 mhz ? sub-clock oscillator frequency: 32.768 khz ? pll circuit input: 4 mhz to 12.5 mhz ? on-chip low- and high-speed oscillators, dedicated on-chip low-speed oscillator for the iwdt ? usb-dedicated pll circuit: 4, 6, 8, or 12 mhz 54 mhz can be set for the system clock and 48 mhz for the usb clock ? generation of a dedicated 32.768-khz clock for the rtc ? clock frequency accuracy measurement circuit (cac) realtime clock ? adjustment functions (30 seconds, leap year, and error) ? calendar count mode or binary count mode selectable ? time capture function ? time capture on event-signal input through external pins independent watchdog timer ? 15-khz on-chip oscillator produces a dedicated clock signal to drive iwdt operation. useful functions fo r iec60730 compliance ? self-diagnostic and disconnection-detection assistance functions for the a/d converter, clock frequency accuracy measurement circuit, independent watchdog timer, ram test assistance functions using the doc, etc. external address space ? four cs areas (4 16 mbytes) ? 8- or 16-bit bus space is selectable per area mpc ? input/output functions selectable from multiple pins up to 14 communication functions ? usb 2.0 host/function/on-the-go (otg) (one channel), full-speed = 12 mbps, low-speed = 1.5 mbps, isochronous transfer, and bc (battery charger) supported ? can (one channel) compliant to iso11898-1: transfer at up to 1 mbps ? sci with many useful functions (up to 7 channels) asynchronous mode, clock synchronous mode, smart card interface reduction of errors in communications using the bit modulation function ? irda interface (one channel, in cooperation with the sci5) ? i 2 c bus interface: transfer at up to 400 kbps, capable of smbus operation (one channel) ? rspi (one channel): transfer at up to 16 mbps ? serial sound interface (one channel) ? sd host interface (optional: one channel) sd memory/ sdio 1-bit or 4-bit sd bus supported note: 48-pin packages support 1-bit mode only up to 20 extended-function timers ? 16-bit mtu: input capture, output compare, complementary pwm output, phase counting mode (six channels) ? 16-bit tpu: input capture, output compare, phase counting mode (six channels) ? 8-bit tmr (four channels) ? 16-bit compare-match timers (four channels) 12-bit a/d converter ? capable of conversion within 0.83 s ? 24 channels ? sampling time can be set for each channel ? self-diagnostic function and analog input disconnection detection assistance function 12-bit d/a converter ? two channels capacitive touch sensing unit ? self-capacitance method: a single pin configures a single key, supporting up to 24 keys ? mutual capacitance method: matrix configuration with 24 pins, supporting up to 144 keys analog comparator ? two channels two units general i/o ports ? 5-v tolerant, open drain, input pull-up, switching of driving capacity security functions (tsip-lite) ? unauthorized access to the encryption engine is disabled and imposture and falsification of information are prevented ? safe management of keys ? 128- or 256-bit key length of aes for ecb, cbc, gcm, others ? true random number generator temperature sensor operating temperature range ?? 40 to +85 ? c ?? 40 to +105 ?c applications ? general industrial and consumer equipment plqp0100kb-b 14 14 mm, 0.5 mm pitch plqp0064kb-c 10 10 mm, 0.5 mm pitch PLQP0048KB-B 7 7 mm, 0.5 mm pitch pwqn0064kc-a 9 9 mm, 0.5 mm pitch pwqn0048kb-a 7 7 mm, 0.5 mm pitch ptlg0100ka-a 5.5 5.5 mm, 0.5 mm pitch pwlg0064ka-a 5 5 mm, 0.5 mm pitch 54-mhz 32-bit rx mcus, built-in fpu, 88.56 dmips, up to 512-kb flash memory, various communication functions including usb 2.0 full-speed host/function/otg, can, sd host interface, serial sound interface, capacitive touch sensing uni t, 12-bit a/d, 12-bit d/a, rtc, aes, mpu security functions r01ds0261ej0110 rev.1.10 oct 30, 2015
r01ds0261ej0110 rev.1.10 page 2 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications, and table 1.2 gives a comparison of the functions of the products in different packages. table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the p ackage type. for details, see table 1.2, comparison of functions for different packages . table 1.1 outline of specifications (1/4) classification module/function description cpu cpu ? maximum operating frequency: 54 mhz ? 32-bit rx cpu (rx v2) ? minimum instruction execution time: one instruction per clock cycle ? address space: 4-gbyte linear ? register set general purpose: sixteen 32-bit registers control: ten 32-bit registers accumulator: two 72-bit registers ? basic instructions: 75 (variable-length instruction format) ? floating-point instructions: 11 ? dsp instructions: 23 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32-bit 32-bit 64-bit ? on-chip divider: 32-bit 32-bit 32 bits ? barrel shifter: 32 bits ? memory protection unit (mpu) fpu ? single precision (32-bit) floating point ? data types and floating-point exceptions in conformance with the ieee754 standard memory rom ? capacity: 128/256/384/512 kbytes ? up to 32 mhz: no-wait memory access 32 to 54 mhz: wait state required. no wait state if the instruction is served by a rom accelerator hit. ? programming/erasing method: serial programming (asynchronous serial communication/usb communication), self-programming ram ? capacity: 32/64 kbytes ? 54 mhz, no-wait memory access e2 dataflash ? capacity: 8 kbytes ? number of erase/write cycles: 1,000,000 (typ) mcu operating mode single-chip mode, on-chip rom enabled expansion mode, and on-chip rom disabled expansion mode (software switching) clock clock generation circuit ? main clock oscillator, sub-clock oscillator, low-s peed on-chip oscillator, high-speed on-chip oscillator, pll frequency synthesizer, usb-dedicated pll frequency synthesizer, and iwdt-dedicated on-chip oscillator ? oscillation stop detection: available ? clock frequency accuracy measurement circuit (cac) ? independent settings for the system clock (iclk), peripheral module clock (pclk), external bus clock (bclk), and flashif clock (fclk) the cpu and system sections such as other bus masters run in synchronization with the system clock (iclk): 54 mhz (at max.) mtu2a runs in synchronization with the pclka: 54 mhz (at max.) the adclk for the s12ad runs in synchronization with the pclkd: 54 mhz (at max.) peripheral modules other than mtu2a and s12ade run in synchronization with the pclkb: 32 mhz (at max.) devices connected to external buses run in synchronization wit h the bclk: 32 mhz (at max.) the flash peripheral circuit runs in sync hronization with the fclk: 32 mhz (at max.) resets res# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog timer reset, and software reset voltage detection voltage detection circuit (lvdab) ? when the voltage on vcc falls below the voltage detection level, an internal reset or internal interrupt is generated. voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
r01ds0261ej0110 rev.1.10 page 3 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview low power consumption low power consumption functions ? module stop function ? three low power consumption modes sleep mode, deep sleep mode, and software standby mode ? low power timer that operates during the software standby state function for lower operating power consumption ? operating power control modes high-speed operating mode, middle-speed operating mode, and low-speed operating mode interrupt interrupt controller (icub) ? interrupt vectors: 167 ? external interrupts: 9 (nmi, irq0 to irq7 pins) ? non-maskable interrupts: 7 (nmi pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, wdt interrupt, iwdt interrupt, and vbatt power monitoring interrupt) ? 16 levels specifiable for the order of priority external bus extension ? the external address space can be divided into four areas (cs0 to cs3), each with independent control of access settings. capacity of each area: 16 mbytes (cs0 to cs3) a chip-select signal (cs0# to cs3#) can be output for each area. each area is specifiable as an 8-bit or 16-bit bus space the data arrangement in each area is selectable as little or big endian (only for data). bus format: separate bus, multiplex bus ? wait control ? write buffer facility dma dma controller (dmaca) ? 4 channels ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, external in terrupts, and interrupt requests from peripheral functions data transfer controller (dtca) ? transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: interrupts ? chain transfer function i/o ports general i/o ports 100-pin /64-pin /48-pin i/o: 79/43/30 (rx231 group), 83/47/34 (rx230 group) ? input: 1/1/1 pull-up resistors: 79/43/30(rx231 group), 83/47/34 (rx230 group) ? open-drain outputs: 58/34/26 ? 5-v tolerance: 5/3/3 event link controller (elc) ? event signals of 61 types can be directly connected to the module ? operations of timer modules are selectable at event input ? capable of event link operation for port b and port e multi-function pin controller (mpc) capable of selecting the input/output function from multiple pins timers 16-bit timer pulse unit (tpua) ? (16 bits 6 channels) 1 unit ? maximum of 16 pulse-input/output possible ? select from among seven or eight coun ter-input clock signals for each channel ? supports the input capture/output compare function ? output of pwm waveforms in up to 15 phases in pwm mode ? support for buffered operation, phase-counting mode (two-phase encoder input) and cascade connected operation (32 bits 2 channels) depending on the channel. ? capable of generating conversion start triggers for the a/d converters ? signals from the input capture pins are input via a digital filter ? clock frequency measuring method multi-function timer pulse unit 2 (mtu2a) ? (16 bits 6 channels) 1 unit ? up to 16 pulse-input/output lines and three pulse -input lines are available based on the six 16-bit timer channels ? select from among eight or seven counter-input clock signals for each channel (pclk/1, pclk/4, pclk/16, pclk/64, pclk/256, pclk/1024, mt clka, mtclkb, mtclkc, mtclkd) other than channel 5, for which only four signals are available. ? input capture function ? 21 output compare/input capture registers ? pulse output mode ? complementary pwm output mode ? reset synchronous pwm mode ? phase-counting mode ? capable of generating conversion start triggers for the a/d converter port output enable 2 (poe2a) controls the high-impedance state of the mtu?s waveform output pins compare match timer (cmt) ? (16 bits 2 channels) 2 units ? select from among four clock signals (pclk/8, pclk/32, pclk/128, pclk/512) watchdog timer (wdta) ? 14 bits x 1 channel ? select from among six counter-input clock signals (pclk/4, pclk/64, pclk/128, pclk/512, pclk/ 2048, pclk/8192) table 1.1 outline of specifications (2/4) classification module/function description
r01ds0261ej0110 rev.1.10 page 4 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview timers independent watchdog timer (iwdta) ? 14 bits 1 channel ? count clock: dedicated low-speed on-chip oscillator for the iwdt frequency divided by 1, 16, 32, 64, 128, or 256 realtime clock (rtce) ? clock source: sub-clock ? time/calendar ? interrupts: alarm interrupt, periodic interrupt, and carry interrupt ? time-capture facility for three values low power timer (lpt) ? 16 bits 1 channel ? clock source: sub-clock, dedicated low-speed on-chip oscillator for the iwdt frequency divided by 2, 4, 8, 16, or 32 8-bit timer (tmr) ? (8 bits 2 channels) 2 units ? seven internal clocks (pclk/1, pclk/2, pclk/8, pclk/32, pclk/ 64, pclk/1024, and pclk/8192) and an external clock can be selected ? pulse output and pwm output with any duty cycle are available ? two channels can be cascaded and used as a 16-bit timer communication functions serial communications interfaces (scig, scih) ? 7 channels (channel 0, 1, 5, 6, 8, 9: scig, channel 12: scih) ? scig serial communications modes: asynchronous, clock synchronous, and smart-card interface multi-processor function on-chip baud rate generator allows selection of the desired bit rate choice of lsb-first or msb-first transfer average transfer rate clock can be input fr om tmr timers for sci5, sci6, and sci12 start-bit detection: level or edge detection is selectable. simple i 2 c simple spi 9-bit transfer mode bit rate modulation event linking by the elc (only on channel 5) ? scih (the following functions are added to scig) supports the serial communications protocol, whic h contains the start frame and information frame supports the lin format irda interface (irda) ? 1 channel (sci5 used) ? supports encoding/decoding of waveforms conforming to irda standard 1.0 i 2 c bus interface (riica) ? 1 channel ? communications formats: i 2 c bus format/smbus format ? master mode or slave mode selectable ? supports fast mode serial peripheral interface (rspia) ? 1 channel ? transfer facility using the mosi (master out, slave in), miso (master in, slave out), ssl (slave select), and rspck (rspi clock) enables serial transfer through spi operation (four lines) or clock-synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats ? choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception usb 2.0 host/function module (usbd) ? usb device controller (udc) and transceiver for usb 2.0 are incorporated. ? host/function module: 1 port ? compliant with usb version 2.0 ? transfer speed: full-speed (12 mbps), low-speed (1.5 mbps) ? otg (on-the-go) is supported. ? isochronous transfer is supported. ? bc1.2 (battery charging specification revision 1.2) is supported. ? internal power supply for usb (allows operation without external power input to the vcc_usb pin when vcc = 4.0 to 5.5v) can module (rscan) ? 1 channel ? compliance with the iso11898-1 specification (standard frame and extended frame) ? 16 message boxes table 1.1 outline of specifications (3/4) classification module/function description
r01ds0261ej0110 rev.1.10 page 5 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview communication functions serial sound interface (ssi) ? 1 channel ? capable of duplex communications ? various serial audio formats supported ? master/slave function supported ? programmable word clock or bit clock generation function ? 8/16/18/20/22/24/32-bit data formats supported ? on-chip 8-stage fifo for transmission/reception ? supports ws continue mode in which the ssiws signal is not stopped. sd host interface (sdhia) ? 1 channel ? transfer speed : default speed mode (8mb/s) ? sd memory card interface (1 bit / 4bits sd bus) ? mmc, emmc backward-compatible are supported. ? sd specifications part 1: compliant with physical layer specification ver.3.01 (not support ddr) part e1: sdio specification ver. 3.00 ? compliant with usb version 2.0 ? error check function: crc7 (command), crc16 (data) ? interrupt source: card access interrupt, sdio access interrupt, card detection interrupt, sd buffer access interrupt ? dma transfer sources: sd_bufwrite, sd_buf read ? card detection, write protection security functions ? access management circuit ? encryption engine 128- or 256-bit key sizes of aes block cipher mode of operation: gcm, ecb, cbc, cmac, xts, ctr, gctr ? hash function ? true random number generator ? unique id 12-bit a/d converter (s12ade) ? 12 bits (24 channels 1 unit) ? 12-bit resolution ? minimum conversion time: 0.83 s per channel when the adclk is operating at 54 mhz ? operating modes scan mode (single scan mode, continuous scan mode, and group scan mode) group a priority control (only for group scan mode) ? sampling variable sampling time can be set up for each channel. ? self-diagnostic function ? double trigger mode (a/d conversion data duplicated) ? detection of analog input disconnection ? a/d conversion start conditions a software trigger, a trigger from a timer (mtu, tpu), an external trigger signal, or elc ? event linking by the elc temperature sensor (tempsa) ? 1 channel ? the voltage output from the temperature sensor is co nverted into a digital value by the 12-bit a/d converter. 12-bit d/a converter (r12daa) ? 2 channels ? 12-bit resolution ? output voltage: 0.4 to avcc0-0.5v crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-firs t or msb-first communications is selectable. comparator b (cmpba) ? 2 channels 2 units ? function to compare the reference voltage and the analog input voltage ? window comparator operation or standard comparator operation is selectable capacitive touch sensing unit (ctsu) detection pin: 24 channels data operation circuit (doc) comparison, addition, and subtraction of 16-bit data power supply voltages/operating frequencies vcc = 1.8 to 2.4 v: 8 mhz, vcc = 2.4 to 2.7 v: 16 mhz, vcc = 2.7 to 5.5 v: 54 mhz operating temperature range d version: ? 40 to +85c, g version: ? 40 to +105c packages 100-pin tflga (ptlg0100ka-a) 5.5 5.5 mm, 0.5 mm pitch 100-pin lfqfp (plqp0100kb-b) 14 14 mm, 0.5 mm pitch 64-pin wflga (pwlg0064ka-a) 5 5 mm, 0.5 mm pitch 64-pin hwqfn (pwqn0064kc-a) 9 9 mm, 0.5 mm pitch 64-pin lfqfp (plqp0064kb-c) 10 10 mm, 0.5 mm pitch 48-pin hwqfn (pwqn0048kb-a) 7 7 mm, 0.5 mm pitch 48-pin lfqfp (PLQP0048KB-B) 7 7 mm, 0.5 mm pitch on-chip debugging system e1 emulator (fine interface) table 1.1 outline of specifications (4/4) classification module/function description
r01ds0261ej0110 rev.1.10 page 6 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview table 1.2 comparison of functions for different packages module/functions rx230 group rx231 group 100 pins 64 pins 48 pins 100 pins 64 pins 48 pins external bus external bus 16 bit n ot supported 16 bit not supported interrupts external interrupts nmi, irq0 to irq7 nmi, irq0 to irq2, irq4 to irq7 nmi, irq0, irq1, irq4 to irq7 nmi, irq0 to irq7 nmi, irq0 to irq2, irq4 to irq7 nmi, irq0, irq1, irq4 to irq7 dma dma controller 4 channels (dmac0 to dmac3) 4 channels (dmac0 to dmac3) data transfer controll er available available timers 16-bit timer pulse unit 6 channels (tpu0 to tpu5) 6 channels (tpu0 to tpu5) multi-function timer pulse unit 2 6 channels (mtu0 to mtu5) 6 channels (mtu0 to mtu5) port output enable 2 poe0# to poe3#, poe8# poe0# to poe3#, poe8# 8-bit timer 2 channels 2 units 2 channels 2 units compare match timer 2 channel s 2 units 2 channels 2 units low power timer 1 channel 1 channel realtime clock available not supported available not supported watchdog timer available available independent watchdog timer available available communication functions serial communications interfaces (scig) 6 channels (sci0, 1, 5, 6, 8, 9) 5 channels (sci1, 5, 6, 8, 9) 4 channels (sci1, 5, 6, 8) 6 channels (sci0, 1, 5, 6, 8, 9) 5 channels (sci1, 5, 6, 8, 9) 4 channels (sci1, 5, 6, 8) irda interface 1 channel (sci5) 1 channel (sci5) serial communications interfaces (scih) 1 channel (sci12) 1 channel (sci12) i 2 c bus interface 1 channel 1 channel can module not supported 1 channel serial peripheral interface 1 channel 1 channel usb 2.0 host/function module not supported 1 channel serial sound interface 1 channel 1 channel sd host interface not supported 1 channel capacitive touch sensing unit 24 channels 10 channels 6 channels 24 channels 10 channels 6 channels 12-bit a/d converter (including high-precision channels) 24 channels (8 channels) 12 channels (6 channels) 8 channels (4 channels) 24 channels (8 channels) 12 channels (6 channels) 8 channels (4 channels) temperature sensor available available d/a converter 2 channels not supported 2 channels not supported crc calculator available available event link controll er available available comparator b 4 channels 4 channels packages 100-pin tflga 100-pin lfqfp 64-pin wflga 64-pin hwqfn 64-pin lfqfp 48-pin hwqfn 48-pin lfqfp 100-pin tflga 100-pin lfqfp 64-pin wflga 64-pin hwqfn 64-pin lfqfp 48-pin hwqfn 48-pin lfqfp
r01ds0261ej0110 rev.1.10 page 7 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview 1.2 list of products table 1.3 and table 1.4 are a list of products, and figure 1.1 shows how to read the product part no., memory capacity, and package type. table 1.3 list of products: d version (t a = ?40 to +85c) (1/2) group part no. order part no. package rom capacity ram capacity e2 dataflash operating frequency security function sdhi can operating temperature rx231 r5f52318adla r5f52318adla#20 ptlg0100ka-a 512 kbytes 64 kbytes 8 kbytes 54 mhz not available not available available ? 40 to +85c r5f52318bdla r5f52318bdla#20 available available available r5f52318adfp r5f52318adfp#30 plqp0100kb-b not available not available available r5f52318bdfp r5f52318bdfp#30 available available available r5f52318adnd r5f52318adnd#u0 pwqn0064kc-a not available not available available r5f52318bdnd r5f52318bdnd#u0 available available available r5f52318adfm r5f52318adfm#30 plqp0064kb-c not available not available available r5f52318bdfm r5f52318bdfm#30 available available available r5f52318adne r5f52318adne#u0 pwqn0048kb-a not available not available available r5f52318bdne r5f52318bdne#u0 available available available r5f52318adfl r5f52318adfl#30 PLQP0048KB-B not available not available available r5f52318bdfl r5f52318bdfl#30 available available available r5f52317adla r5f52317adla#20 ptlg0100ka-a 384 kbytes not available not available available r5f52317bdla r5f52317bdla#20 available available available r5f52317adfp r5f52317adfp#30 plqp0100kb-b not available not available available r5f52317bdfp r5f52317bdfp#30 available available available r5f52317adnd r5f52317adnd#u0 pwqn0064kc-a not available not available available r5f52317bdnd r5f52317bdnd#u0 available available available r5f52317adfm r5f52317adfm#30 plqp0064kb-c not available not available available r5f52317bdfm r5f52317bdfm#30 available available available r5f52317adne r5f52317adne#u0 pwqn0048kb-a not available not available available r5f52317bdne r5f52317bdne#u0 available available available r5f52317adfl r5f52317adfl#30 PLQP0048KB-B not available not available available r5f52317bdfl r5f52317bdfl#30 available available available r5f52316adla r5f52316adla#20 ptlg0100ka-a 256 kbytes 32 kbytes not available not ava ilable available r5f52316cdla r5f52316cdla#20 not available not available not available r5f52316adfp r5f52316adfp#30 plqp0100kb-b not available not available available r5f52316cdfp r5f52316cdfp#30 not available not available not available r5f52316cdlf r5f52316cdlf#u0 pwlg0064ka-a not available not available not available r5f52316adnd r5f52316adnd#u0 pwqn0064kc-a not available not available available r5f52316cdnd r5f52316cdnd#u0 not available not available not available r5f52316adfm r5f52316adfm#30 plqp0064kb-c not available not available available r5f52316cdfm r5f52316cdfm#30 not available not available not available r5f52316adne r5f52316adne#u0 pwqn0048kb-a not available not available available r5f52316cdne r5f52316cdne#u0 not available not available not available r5f52316adfl r5f52316adfl#30 PLQP0048KB-B not available not available available r5f52316cdfl r5f52316cdfl#30 not available not available not available
r01ds0261ej0110 rev.1.10 page 8 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview rx231 r5f52315adla r5f52315adla#20 ptlg0100ka-a 128 kbytes 32 kbytes 8 kbytes 54 mhz not available not available available ? 40 to +85c r5f52315cdla r5f52315cdla#20 not available not available not available r5f52315adfp r5f52315adfp#30 plqp0100kb-b not available not available available r5f52315cdfp r5f52315cdfp#30 not available not available not available r5f52315cdlf r5f52315cdlf#20 pwlg0064ka-a not available not available not available r5f52315adnd r5f52315adnd#u0 pwqn0064kc-a not available not available available r5f52315cdnd r5f52315cdnd#u0 not available not available not available r5f52315adfm r5f52315adfm#30 plqp0064kb-c not available not available available r5f52315cdfm r5f52315cdfm#30 not available not available not available r5f52315adne r5f52315adne#u0 pwqn0048kb-a not available not available available r5f52315cdne r5f52315cdne#u0 not available not available not available r5f52315adfl r5f52315adfl#30 PLQP0048KB-B not available not available available r5f52315cdfl r5f52315cdfl#30 not available not available not available rx230 r5f52306adla r5f52306adla#20 ptlg0100ka-a 256 kbytes 32 kbytes 8 kbytes 54 mhz not available not available not available ? 40 to +85c r5f52306adfp r5f52306adfp#30 plqp0100kb-b not available not available not available r5f52306adlf r5f52306adlf#20 pwlg0064ka-a not available not available not available r5f52306adnd r5f52306adnd#u0 pwqn0064kc-a not available not ava ilable not available r5f52306adfm r5f52306adfm#30 plqp0064kb-c not available not available not available r5f52306adne r5f52306adne#u0 pwqn0048kb-a not available not available not available r5f52306adfl r5f52306adfl#30 PLQP0048KB-B not available not available not available r5f52305adla r5f52305adla#20 ptlg0100ka-a 128 kbytes not available not available not available r5f52305adfp r5f52305adfp#30 plqp0100kb-b not available not available not available r5f52305adlf r5f52305adlf#20 pwlg0064ka-a not available not available not available r5f52305adnd r5f52305adnd#u0 pwqn0064kc-a not available not available not available r5f52305adfm r5f52305adfm#30 plqp0064kb-c not available not available not available r5f52305adne r5f52305adne#u0 pwqn0048kb-a not available not available not available r5f52305adfl r5f52305adfl#30 PLQP0048KB-B not available not available not available table 1.3 list of products: d version (t a = ?40 to +85c) (2/2) group part no. order part no. package rom capacity ram capacity e2 dataflash operating frequency security function sdhi can operating temperature
r01ds0261ej0110 rev.1.10 page 9 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview table 1.4 list of products: g version (t a = ?40 to +105c) (1/2) group part no. order part no. package rom capacity ram capacity e2 dataflash operating frequency security function sdhi can operating temperature rx231 r5f52318agfp r5f52318agfp#30 plqp0100kb-b 512 kbytes 64 kbytes 8 kbytes 54 mhz not available not available available ? 40 to +105c r5f52318bgfp r5f52318bgfp#30 available available available r5f52318agnd r5f52318agnd#u0 pwqn0064kc-a not available not available available r5f52318bgnd r5f52318bgnd#u0 available available available r5f52318agfm r5f52318agfm#30 plqp0064kb-c not available not available available r5f52318bgfm r5f52318bgfm#30 available available available r5f52318agne r5f52318agne#u0 pwqn0048kb-a not available not available available r5f52318bgne r5f52318bgne#u0 available available available r5f52318agfl r5f52318agfl#30 PLQP0048KB-B not available not available available r5f52318bgfl r5f52318bgfl#30 available available available r5f52317agfp r5f52317agfp#30 plqp0100kb-b 384 kbytes not available not available available r5f52317bgfp r5f52317bgfp#30 available available available r5f52317agnd r5f52317agnd#u0 pwqn0064kc-a not available not available available r5f52317bgnd r5f52317bgnd#u0 available available available r5f52317agfm r5f52317agfm#30 plqp0064kb-c not available not available available r5f52317bgfm r5f52317bgfm#30 available available available r5f52317agne r5f52317agne#u0 pwqn0048kb-a not available not available available r5f52317bgne r5f52317bgne#u0 available available available r5f52317agfl r5f52317agfl#30 PLQP0048KB-B not available not available available r5f52317bgfl r5f52317bgfl#30 available available available r5f52316agfp r5f52316agfp#30 plqp0100kb-b 256 kbytes 32 kbytes not available not available available r5f52316cgfp r5f52316cgfp#30 not available not available not available r5f52316agnd r5f52316agnd#u0 pwqn0064kc-a not available not available av ailable r5f52316cgnd r5f52316cgnd#u0 not available not available not available r5f52316agfm r5f52316agfm#30 plqp0064kb-c not available not available available r5f52316cgfm r5f52316cgfm#30 not available not available not available r5f52316agne r5f52316agne#u0 pwqn0048kb-a not available not available available r5f52316cgne r5f52316cgne#u0 not available not available not available r5f52316agfl r5f52316agfl#30 PLQP0048KB-B not available not available available r5f52316cgfl r5f52316cgfl#30 not available not available not available r5f52315agfp r5f52315agfp#30 plqp0100kb-b 128 kbytes not available not available available r5f52315cgfp r5f52315cgfp#30 not available not available not available r5f52315agnd r5f52315agnd#u0 pwqn0064kc-a not available not available available r5f52315cgnd r5f52315cgnd#u0 not available not available not available r5f52315agfm r5f52315agfm#30 plqp0064kb-c not available not available available r5f52315cgfm r5f52315cgfm#30 not available not available not available r5f52315agne r5f52315agne#u0 pwqn0048kb-a not available not available available r5f52315cgne r5f52315cgne#u0 not available not available not available r5f52315agfl r5f52315agfl#30 PLQP0048KB-B not available not available available r5f52315cgfl r5f52315cgfl#30 not available not ava ilable not available
r01ds0261ej0110 rev.1.10 page 10 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview rx230 r5f52306agfp r5f52306agfp#30 plqp0100kb-b 256 kbytes 32 kbytes 8 kbytes 54 mhz not available not available not available ? 40 to +105c r5f52306agnd r5f52306agnd#u0 pwqn0064kc-a not available not available not available r5f52306agfm r5f52306agfm#30 plqp0064kb-c not available not available not available r5f52306agne r5f52306agne#u0 pwqn0048kb-a not available not available not available r5f52306agfl r5f52306agfl#30 PLQP0048KB-B not available not available not available r5f52305agfp r5f52305agfp#30 plqp0100kb-b 128 kbytes not available not available not available r5f52305agnd r5f52305agnd#u0 pwqn0064kc-a not available not available not available r5f52305agfm r5f52305agfm#30 plqp0064kb-c not available not available not available r5f52305agne r5f52305agne#u0 pwqn0048kb-a not available not available not available r5f52305agfl r5f52305agfl#30 PLQP0048KB-B not available not available not available table 1.4 list of products: g version (t a = ?40 to +105c) (2/2) group part no. order part no. package rom capacity ram capacity e2 dataflash operating frequency security function sdhi can operating temperature
r01ds0261ej0110 rev.1.10 page 11 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview figure 1.1 how to read the product part number r5f52318adfm package type, number of pins, and pin pitch fp: lfqfp/100/0.50 fm: lfqfp/64/0.50 fl: lfqfp/48/0.50 la: tflga/100/0.50 lf: wflga/64/0.50 nd: hwqfn/64/0.50 ne: hwqfn/48/0.50 d: operating ambient temperature: ?40 to +85c g: operating ambient temperature: ?40 to +105c chip versions rx231 group a: security function not included, sdhi module not included, can module included b: security function included, sdhi module included, can module included c: security function not included, sdhi module not included, can module not included rx230 group a: usb module not included rom, ram, and e2 dataflash capacity 8: 512 kbytes/64 kbytes/8 kbytes 7: 384 kbyte/64 kbytes/8 kbytes 6: 256 kbytes/32 kbytes/8 kbytes 5: 128 kbytes/32 kbytes/8 kbytes group name 31: rx231 group 30: rx230 group series name rx200 series type of memory f: flash memory version renesas mcu renesas semiconductor product
r01ds0261ej0110 rev.1.10 page 12 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram clock generation circuit rx cpu ram rom port 0 port 1 port 3 port 4 12-bit d/a converter 2 channels riica 1 channel doc rtce mtu2a 6 channels 12-bit a/d converter 24 channels cmt 2 channels (unit 0) rspia 1 channel dtca icub cac scih 1 channel port 5 port a port b port c poe2a usb 2.0 host/function module port 2 temperature sensor port d port h port j external bus dmaca 4 channels comparator b 4 channels tmr 2 channels (unit 0) tmr 2 channels (unit 1) ssi cmt 2 channels (unit 1) mpu tpua 6 channels operand bus instruction bus internal main bus 1 internal main bus 2 bsc scig 6 channels (including irda 1 channel) e2 dataflash crc elc iwdta wdta sdhia rscan ctsu lpt internal peripheral buses 1 to 6 port e icub: interrupt controller dtca: data transfer controller dmaca: dma controller bsc: bus controller wdta: watchdog timer iwdta: independent watchdog timer elc: event link controller crc: crc (cyclic redundanc y check) calculator scig/scih: serial communications interface rspia: serial peripheral interface ssi: serial sound interface riica: i 2 c bus interface tpua: 16-bit timer pulse unit mtu2a: multi-function timer pulse unit 2 poe2a: port output enable 2 cmt: compare match timer rtce: realtime clock doc: data operation circuit cac: clock frequency accuracy measurement circuit ctsu: capacitive touch sensing unit sdhia: sd host interface mpu: memory protection unit tmr: 8-bit timer rscan: can module lpt: low power timer
r01ds0261ej0110 rev.1.10 page 13 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview 1.4 pin functions table 1.5 lists the pin functions. table 1.5 pin functions (1/4) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl ? connect this pin to the vss pin via the 4.7 f smoothing capacitor used to stabilize the internal power supply. pl ace the capacitor close to the pin. vss input ground pin. connect it to the system power supply (0 v). vbatt input backup power pin clock xtal output pins for connecting a crystal. an external clock can be input through the extal pin. extal input bclk output outputs the external bus cl ock for external devices. xcin input input/output pins for the sub-clock oscillator. connec t a crystal between xcin and xcout. xcout output clkout output clock output pin. operating mode control md input pin for setting the operating mode. the signal levels on this pin must not be changed during operation. ub input pin used for boot mode (usb interface). upsel input pin used for boot mode (usb interface). system control res# input reset pin. this mcu enter s the reset state when this signal goes low. cac cacref input input pin for the clock fr equency accuracy m easurement circuit. on-chip emulator fined i/o fine interface pin. address bus a0 to a23 output output pins for the address. data bus d0 to d15 i/o input and output pins for the bidirectional data bus. multiplexed bus a0/d0 to a15/d15 i/o address/data multiplexed bus bus control rd# output strobe signal which indicates that reading from the external bus interface space is in progress. wr# output strobe signal which indicates that writing to the external bus interface space is in progress, in single-write strobe mode. wr0#, wr1# output strobe signals which indicate t hat either group of data bus pins (d7 to d0, and d15 to d8) is valid in writing to the external bus interface space, in byte strobe mode. bc0#, bc1# output strobe signals wh ich indicate that either group of data bus pins (d7 to d0 and d15 to d8) is valid in access to the external bus interface space, in single-write strobe mode. cs0# to cs3# output select signals for areas 0 to 3. wait# input input pin for wait request signal s in access to the external space. ale output address latch signal when addr ess/data multiplexed bus is selected. lvd cmpa2 input detection target voltage pin for voltage detection 2. interrupts nmi input non-maskable interrupt request pin. irq0 to irq7 input interrupt request pins.
r01ds0261ej0110 rev.1.10 page 14 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview 16-bit timer pulse unit tioca0, tiocb0 tiocc0, tiocd0 i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins. tioca1, tiocb1 i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins. tioca2, tiocb2 i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins. tioca3, tiocb3 tiocc3, tiocd3 i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins. tioca4, tiocb4 i/o the tgra4 and tgrb4 input capture input/output compare output/pwm output pins. tioca5, tiocb5 i/o the tgra5 and tgrb5 input capture input/output compare output/pwm output pins. tclka, tclkb tclkc, tclkd input input pins for external clock signals. multi-function timer pulse unit 2 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/pwm output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/external pulse input pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for the external clock. port output enable 2 poe0# to poe3#, poe8# input input pins for request signals to place the mtu pins in the high impedance state. realtime clock rtcout output output pin for the 1-hz/64-hz clock. rtcic0 to rtcic2 input time capture event input pins. 8-bit timer tmo0 to tmo3 output compare match output pins. tmci0 to tmci3 input input pins for the external clock to be input to the counter. tmri0 to tmri3 input counter reset input pins. serial communications interface (scig) ? asynchronous mode/clock synchronous mode sck0, sck1, sck5, sck6, sck8, sck9 i/o input/output pins for the clock. rxd0, rxd1, rxd5, rxd6, rxd8, rxd9 input input pins for received data. txd0, txd1, txd5, txd6, txd8, txd9 output output pins for transmitted data. cts0#, cts1#, cts5#, cts6#, cts8#, cts9# input input pins for controlling the start of transmission and reception. rts0#, rts1#, rts5#, rts6#, rts8#, rts9# output output pins for controlling the start of transmission and reception. ? simple i 2 c mode sscl0, sscl1, sscl5, sscl6, sscl8, sscl9 i/o input/output pins for the i 2 c clock. ssda0, ssda1, ssda5, ssda6, ssda8, ssda9 i/o input/output pins for the i 2 c data. table 1.5 pin functions (2/4) classifications pin name i/o description
r01ds0261ej0110 rev.1.10 page 15 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview serial communications interface (scig) ? simple spi mode sck0, sck1, sck5, sck6, sck8, sck9 i/o input/output pins for the clock. smiso0, smiso1, smiso5, smiso6, smiso8, smiso9 i/o input/output pins for slave transmit data. smosi0, smosi1, smosi5, smosi6, smosi8, smosi9 i/o input/output pins for master transmit data. ss0#, ss1#, ss5#, ss6#, ss8#, ss9# input slave-select input pins. irda interface irtxd5 output data output pin in the irda format. irrxd5 input data input pin in the irda format. serial communications interface (scih) ? asynchronous mode/clock synchronous mode sck12 i/o input/output pin for the clock. rxd12 input input pin for receiving data. txd12 output output pin for transmitting data. cts12# input input pin for controlling the start of transmission and reception. rts12# output output pin for controlling the start of transmission and reception. ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock. ssda12 i/o input/output pin for the i 2 c data. ? simple spi mode sck12 i/o input/output pin for the clock. smiso12 i/o input/output pin for slave transmit data. smosi12 i/o input/output pin for master transmit data. ss12# input slave-select input pin. ? extended serial mode rxdx12 input input pin for data reception by scif. txdx12 output output pin for data transmission by scif. siox12 i/o input/output pin for data reception or transmission by scif. i 2 c bus interface scl i/o input/output pin for i 2 c bus interface clocks. bus can be directly driven by the n-channel open drain output. sda i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the n-channel open drain output. serial peripheral interface rspcka i/o input/output pin for the rspi clock. mosia i/o input/output pin for transmitting data from the rspi master. misoa i/o input/output pin for transmitting data from the rspi slave. ssla0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 output output pins to select the slave for the rspi. serial sound interface ssisck0 i/o ssi serial bit clock pin. ssiws0 i/o word selection pin. ssitxd0 output serial data output pin. ssirxd0 input serial data input pin. audio_mclk input master clock pin for audio. can module crxd0 input input pin ctxd0 output output pin sd host interface sdhi_clk output sd clock output pin sdhi_cmd i/o sd command output, response input signal pin table 1.5 pin functions (3/4) classifications pin name i/o description
r01ds0261ej0110 rev.1.10 page 16 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview sd host interface sdhi_d3 to sd_d0 i/o sd data bus pins sdhi_cd input sd card detection pin sdhi_wp input sd write-protect signal usb 2.0 host/ function module vcc_usb input power supply pin for usb. connect this pin to vcc. vss_usb input ground pin for usb. connect this pin to vss. usb0_dp i/o d+ i/o pin of the usb on-chip transceiver. usb0_dm i/o d- i/o pin of the usb on-chip transceiver. usb0_vbus input usb cable connection monitor pin. usb0_exicen output low-power control signal for the otg chip. usb0_vbusen output vbus (5 v) supply enable signal for the otg chip. usb0_ovrcura, usb0_ovrcurb input external overcurrent detection pins. usb0_id input mini-ab connector id input pin during operation in otg mode. 12-bit a/d converter an000 to an007, an016 to an031 input input pins for the analog signals to be processed by the a/d converter. adtrg0# input input pin for the external trigger signal that start the a/d conversion. 12-bit d/a converter da0, da1 output analog output pins of the d/a converter. comparator b cmpb0 to cmpb3 input input pin for the analog signal to be processed by comparator b. cvrefb0 to cvrefb3 input analog reference voltage supply pin for comparator b. cmpob0 to cmpob3 output output pin for comparator b. ctsu ts0 to ts9, ts12, ts13, ts15 to ts20, ts22, ts23, ts27, ts30, ts33, ts35 output electrostatic capacitance measurement pins (touch pins). tscap output lpf connection pin. analog power supply avcc0 input analog voltage supply pin for the 12-bit a/d converter and d/a converter. connect this pin to vcc when not using the 12-bit a/d converter and d/a converter. avss0 input analog ground pin for the 12-bit a/d converter and d/a converter. connect this pin to vss when not using the 12-bit a/d converter and d/a converter. vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter. vrefl0 input analog reference ground pin for the 12-bit a/d converter. vrefh input analog reference voltage supply pin for the 12-bit d/a converter. vrefl input analog reference ground pin for the 12-bit d/a converter. i/o ports p03, p05, p07 i/o 3-bit input/output pins. p12 to p17 i/o 6-bit input/output pins. p20 to p27 i/o 8-bit input/output pins. p30 to p37 i/o 8-bit input/output pins (p35 input pin). p40 to p47 i/o 8-bit input/output pins. p50 to p55 i/o 6-bit input/output pins. pa0 to pa7 i/o 8-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pc0 to pc7 i/o 8-bit input/output pins. pd0 to pd7 i/o 8-bit input/output pins. pe0 to pe7 i/o 8-bit input/output pins. ph0 to ph3 i/o 4-bit input/output pins. pj3 i/o 1-bit input/output pin. table 1.5 pin functions (4/4) classifications pin name i/o description
r01ds0261ej0110 rev.1.10 page 17 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview 1.5 pin assignments figure 1.3 to figure 1.9 show the pin assignments. table 1.6 to table 1.10 show the lists of pins and pin functions. figure 1.3 pin assignments of the 100-pin tflga (upper perspective view) pe2 rx230 group, rx231 group ptlg0100ka-a (100-pin tflga) (upper perspective view) pe1 pe0 pd4 pd0 p43 vrefl0 p07 vrefh p05 pe3 pd7 pd6 pd3 pd1 p44 p40 avcc0 avss0 p03 pe4 pe5 pd5 pd2 p47 p42 vrefh0 pj3 vrefl vcl pa0 pa1 pe7 pe6 p46 p45 vbatt md xcout xcin pa3 pa5 pa4 pa6 pa2 p41 p34 res# vss p37/ xtal vss pa7 pb0 pb2 pb3 p12 p32 p35 vcc p36/ extal vcc pb1 pb4 pb5 p52 p53 p27 p30 p31 p33 pb7 pb6 pc6 pc7 p54 p55 p15 p16 p25 p26 p17 pc1 pc0 pc4 p50 vcc_ usb/ph3 *1 vss_ usb/ph0 *1 p13 p21 p24 pc2 pc3 pc5 p51 usb0_ dp/ph1 *1 usb0_ dm/ph2 *1 p14 p20 p22 p23 k j h g f e d c b a 10987654321 k j h g f e d c b a 10987654321 note: this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (100-pin tflga)?. note: for the position of a1 pin in the package, see ?package dimensions?. note 1. rx230: ph0, ph1, ph2, ph3 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb
r01ds0261ej0110 rev.1.10 page 18 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview figure 1.4 pin assignments of the 100-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pe0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 p47 p46 p45 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p07 avss0 pe1 p44 pc2 pc4 pc5 pc6 pc7 p50 p51 p52 p53 p54 p55 vss_usb/ph0 *1 usb0_dp/ph1 *1 vcc_usb/ph3 *1 p12 p13 p14 p15 p16 p17 p20 p21 p22 pc3 usb0_dm/ph2 *1 pe3 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vss vcc pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pe4 pb0 vrefh vrefl pj3 vcl vbatt md xcin xcout res# p37/xtal vss p36/extal p35 p34 p33 p32 p31 p30 p27 p26 p25 p23 p03 vcc pe2 p05 p24 rx230 group, rx231 group plqp0100kb-b (100-pin lqfp) (top view) note: this figure indicates the power supply pins and i /o port pins. for the pin configuration, see the table ?list of pins and pin functions (100-pin lqfp)?. note 1. rx230: ph0, ph1, ph2, ph3 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb
r01ds0261ej0110 rev.1.10 page 19 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview figure 1.5 pin assignments of the 64-pin wflga a b c d e f g h 1 2 3 4 5 6 7 8 rx230 group, rx231 group pwlg0064ka-a (64-pin wflga) (upper perspective view) p05 avcc0 vrefh0 avss0 p40 vrefl0 p41 p42 p43 p44 vrefh p46 vrefl pe0 pe1 pe2 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6 pb7 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 vss_ usb/ph0 *1 usb0_ dm/ph2 *1 usb0_ dp/ph1 *1 vcc_ usb/ph3 *1 p14 p15 p16 p17 p26 p27 p30 p31 vbatt p35 vcc p36/ extal vss p37/ xtal res# xcout xcin md vcl p03 note: this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (64-pin wflga)?. note: for the position of a1 pin in the package, see ?package dimensions?. note 1. rx230: ph0, ph1, ph2, ph3 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb
r01ds0261ej0110 rev.1.10 page 20 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview figure 1.6 pin assignments of the 64-pin hwqfn 49 rx230 group, rx231 group pwqn0064kc-a (64-pin hwqfn) (top view) pe2 pe1 pe0 vrefl p46 vrefh p44 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p05 avss0 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6 pb7 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 vss_usb/ph0 *1 usb0_dp/ph1 *1 usb0_dm/ph2 *1 vcc_usb/ph3 *1 p14 p15 p16 p17 p03 vcl md xcin xcout res# p37/xtal vss p36/extal vcc p35 vbatt p31 p30 p27 p26 64 50 51 52 53 54 55 56 57 58 59 60 61 62 63 32 17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 note: this figure indicates the pow er supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (64-pin lqfp/hwqfn)?. note: it is recommended to connect an exposed die pad to vss. note 1. rx230: ph0, ph1, ph2, ph3 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb
r01ds0261ej0110 rev.1.10 page 21 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview figure 1.7 pin assignments of the 64-pin lqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx230 group, rx231 group plqp0064kb-c (64-pin lqfp) (top view) pe2 pe1 pe0 vrefl p46 vrefh p44 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p05 avss0 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6 pb7 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 vss_usb/ph0 *1 usb0_dp/ph1 *1 usb0_dm/ph2 *1 vcc_usb/ph3 *1 p14 p15 p16 p17 p03 vcl md xcin xcout res# p37/xtal vss p36/extal vcc p35 vbatt p31 p30 p27 p26 note: this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (64-pin lqfp/hwqfn)?. note 1. rx230: ph0, ph1, ph2, ph3 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb
r01ds0261ej0110 rev.1.10 page 22 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview figure 1.8 pin assignments of the 48-pin lqfp figure 1.9 pin assignments of the 48-pin hwqfn 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 rx230 group, rx231 group PLQP0048KB-B (48-pin lqfp) (top view) pe2 pe1 vrefl p46 vrefh p42 p41 vrefl0 p40 vrefh0 avcc0 avss0 pe3 pe4 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pc4 pc5 pc6 pc7 vss_usb/ph0 *1 usb0_dp/ph1 *1 usb0_dm/ph2 *1 vcc_usb/ph3 *1 p14 p15 p16 p17 vcl md res# p37/xtal vss p36/extal vcc p35 p31 p30 p27 p26 18 17 16 15 14 13 note: this figure indicates the pow er supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (48-pin lqfp/hwqfn)?. note 1. rx230: ph0, ph1, ph2, ph3 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb rx230 group, rx231 group pwqn0048kb-a (48-pin hwqfn) (top view) pe2 pe1 vrefl p46 vrefh p42 p41 vrefl0 p40 vrefh0 avcc0 avss0 pe3 pe4 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pc4 pc5 pc6 pc7 vss_usb/ph0 *1 usb0_dp/ph1 *1 usb0_dm/ph2 *1 vcc_usb/ph3 *1 p14 p15 p16 p17 vcl md res# p37/xtal vss p36/extal vcc p35 p31 p30 p27 p26 37 48 46 45 44 43 42 41 40 39 38 47 24 13 15 16 17 18 19 20 21 22 23 14 1 12 10 9 8 7 6 5 4 3 2 11 36 25 27 28 29 30 31 32 33 34 35 26 note: it is recommended to connect an exposed die pad to vss. note: this figure indicates the pow er supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (48-pin lqfp/hwqfn)?. note 1. rx230: ph0, ph1, ph2, ph3 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb
r01ds0261ej0110 rev.1.10 page 23 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview table 1.6 list of pins and pin functions (100-pin tflga) (1/3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others a1 p05 da1 a2 vrefh a3 p07 adtrg0# a4 vrefl0 a5 p43 an003 a6 pd0 d0[a0/d0] irq0/an024 a7 pd4 d4[a4/d4] poe3# irq4/an028 a8 pe0 d8[a8/d8] sck12 an016 a9 pe1 d9[a9/d9] mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an017/ cmpb0 a10 pe2 d10[a10/d10] mtioc4a rxd12/rxdx12/ smiso12/sscl12 irq7/an018/ cvrefb0 b1 p03 da0 b2 avss0 b3 avcc0 b4 p40 an000 b5 p44 an004 b6 pd1 d1[a1/d1] mtioc4b irq1/an025 b7 pd3 d3[a3/d3] poe8# irq3/an027 b8 pd6 d6[a6/d6] mtic5v/poe1# irq6/an030 b9 pd7 d7[a7/d7] mtic5u/poe0# irq7/an031 b10 pe3 d11[a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12#/ audio_mclk an019/ clkout c1 vcl c2 vrefl c3 pj3 mtioc3c cts6#/rts6#/ss6# c4 vrefh0 c5 p42 an002 c6 p47 an007 c7 pd2 d2[a2/d2] mtioc4d irq2/an026 c8 pd5 d5[a5/d5] mtic5w/poe2# irq5/an029 c9 pe5 d13[a13/d13] mtioc4c/mtioc2b irq5/an021/ cmpob0 c10 pe4 d12[a12/d12] mtioc4d/mtioc1a an020/ cmpa2/ clkout d1 xcin d2 xcout d3 md fined d4 vbatt d5 p45 an005 d6 p46 an006 d7 pe6 d14[a14/d14] irq6/an022 d8 pe7 d15[a15/d15] irq7/an023 d9 pa1 a1 mtioc0b/mtclkc/ tiocb0 sck5/ssla2/ssisck0 d10 pa0 a0/bc0# mtioc4a/tioca0 ssla1 cacref e1 xtal p37 e2 vss e3 res# e4 p34 mtioc0a/tmci3/poe2# sck6 ts0 irq4 e5 p41 an001 e6 pa2 a2 rxd5/smiso5/sscl5/ ssla3/irrxd5 e7 pa6 a6 mtic5v/mtclkb/tmci3/ poe2#/tioca2 cts5#/rts5#/ss5#/ mosia/ssiws0
r01ds0261ej0110 rev.1.10 page 24 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview e8 pa4 a4 mtic5u/mtclka/tmri0/ tioca1 txd5/smosi5/ssda5/ ssla0/ssitxd0/irtxd5 irq5 / cvrefb1 e9 pa5 a5 tiocb1 rspcka e10 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb rxd5/smiso5/sscl5/ ssirxd0/irrxd5 irq6 /cmpb1 f1 extal p36 f2 vcc f3 p35 nmi f4 p32 mtioc0c/tmo3/tiocc0/ rtcout/rtcic2 txd6/smosi6/ssda6/ usb0_vbusen irq2 f5 p12 tmci1 scl irq2 f6 pb3 a11 mtioc0a/mtioc4a/tmo0/ poe3#/tiocd3/tclkd sck6 sdhi_w p f7 pb2 a10 tiocc3/tclkc cts6#/rts6#/ss6# f8 pb0 a8 mtic5w/tioca3 rxd6/smiso6/sscl6/ rspcka sdhi_c md f9 pa7 a7 tiocb2 misoa f10 vss g1 p33 mtioc0d/tmri3/poe3#/ tiocd0 rxd6/smiso6/sscl6 ts1 irq3 g2 p31 mtioc4d/tmci2/rtcic1 cts1#/rts1#/ss1#/ ssisck0 irq1 g3 p30 mtioc4b/tmri3/poe8#/ rtcic0 rxd1/smiso1/sscl1/ audio_mclk irq0/ cmpob3 g4 p27 cs3# mtioc2b/tmci3 sck1/ ssiws0 ts2 cvrefb3 g5 bclk p53 ts17 g6 p52 rd# ts18 g7 pb5 a13 mtioc2a/mtioc1b/ tmri1/poe1#/tiocb4 sck9 sdhi_cd g8 pb4 a12 tioca4 cts9#/rts9#/ss9# g9 pb1 a9 mtioc0c/mtioc4c/ tmci0/tiocb3 txd6/smosi6/ssda6 sdhi_cl k irq4/ cmpob1 g10 vcc h1 p26 cs2# mtioc2a/tmo1 txd1/smosi1/ssda1/ ssirxd0 ts3 cmpb3 h2 p25 cs1# mtioc4c/mtclkb/ tioca4 ts4 adtrg0# h3 p16 mtioc3c/mtioc3d/ tmo2/tiocb1/tclkc/ rtcout txd1/smosi1/ssda1/ mosia/scl usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6/ adtrg0# h4 p15 mtioc0b/mtclkb/tmci2/ tiocb2/tclkb rxd1/smiso1/sscl1/ crxd0 ts12 irq5/cmpb2 h5 p55 wait# mtioc4d/tmo3 crxd0 ts15 h6 p54 ale mtioc4b/tmci1 ctxd0 ts16 h7 ub pc7 a23/cs0# mtioc3a/mtcl kb/tmo2 txd8/smosi8/ssda8/ misoa cacref h8 pc6 a22/cs1# mtioc3c/mtclka/tmci2 rxd8/smiso8/sscl8/ mosia ts22 h9 pb6 a14 mtioc3d/tioca5 rxd9/smiso9/sscl9 sdhi_d1 h10 pb7 a15 mtioc3b/tiocb5 txd9/smosi9/ssda9 sdhi_d2 j1 p24 cs0# mtioc4a/mtclka/tmri1/ tiocb4 usb0_vbusen ts5 j2 p21 mtioc1b/tmci0/tioca3 rxd0/smiso0/sscl0/ usb0_exicen/ssiws0 ts8 j3 p17 mtioc3a/mtioc3b/tmo1/ poe8#/tiocb0/tclkd sck1/misoa/sda/ ssitxd0 irq7/ cmpob2 j4 p13 mtioc0b/tmo3/tioca5 sda irq3 j5 vss_usb* 1 ph0* 1 cacref* 1 table 1.6 list of pins and pin functions (100-pin tflga) (2/3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others
r01ds0261ej0110 rev.1.10 page 25 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview note 1. rx230: ph0/cacref, ph1/irq0/tmo0, ph2/irq1/tmri0, ph3/tmci0 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb j6 vcc_usb* 1 ph3* 1 tmci0* 1 j7 p50 wr0#/wr# ts20 j8 pc4 a20/cs3# mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ ss8#/ssla0 sdhi_d1 tscap j9 pc0 a16 mtioc3c/tclkc cts5#/rts5#/ss5#/ ssla1 ts35 j10 pc1 a17 mtioc3a/tclkd sck5/ssla2 ts33 k1 p23 mtioc3d/mtclkd/ tiocd3 cts0#/rts0#/ss0#/ ssisck0 ts6 k2 p22 mtioc3b/mtclkc/tmo0/ tiocc3 sck0/ usb0_ovrcurb/ audio_mclk ts7 k3 p20 mtioc1a/tmri0/tio cb3 txd0/smosi0/ssda0/ usb0_id/ssirxd0 ts9 k4 p14 mtioc3a/mtclka/tmri2/ tiocb5/tclka cts1#/rts1#/ss1#/ ctxd0/usb0_ovrcura ts13 irq4/ cvrefb2 k5 ph2* 1 tmri0* 1 usb0_dm* 1 irq1* 1 k6 ph1* 1 tmo0* 1 usb0_dp* 1 irq0* 1 k7 p51 wr1#/bc1#/ wait# ts19 k8 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/tmri2 sck8/rspcka ts23 k9 pc3 a19 mtioc4d/tclkb txd5/smosi5/ssda5/ irtxd5 sdhi_d0 ts27 k10 pc2 a18 mtioc4b/tclka rxd5/smiso5/sscl5/ ssla3/ irrxd5 sdhi_d3 ts30 table 1.6 list of pins and pin functions (100-pin tflga) (3/3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others
r01ds0261ej0110 rev.1.10 page 26 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview table 1.7 list of pins and pin functions (100-pin lfqfp) (1/3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others 1vrefh 2p 0 3 da0 3vrefl 4 pj3 mtioc3c cts6#/rts6#/ss6# 5vcl 6 vbatt 7md fined 8xcin 9 xcout 10 res# 11 xtal p37 12 vss 13 extal p36 14 vcc 15 p35 nmi 16 p34 mtioc0a/tmci3/poe2# sck6 ts0 irq4 17 p33 mtioc0d/tmri3/poe3#/ tiocd0 rxd6/smiso6/sscl6 ts1 irq3 18 p32 mtioc0c/tmo3/tiocc0/ rtcout/rtcic2 txd6/smosi6/ssda6/ usb0_vbusen irq2 19 p31 mtioc4d/tmci2/rtcic1 cts1#/rts1#/ss1#/ ssisck0 irq1 20 p30 mtioc4b/tmri3/poe8#/ rtcic0 rxd1/smiso1/sscl1/ audio_mclk irq0/ cmpob3 21 p27 cs3# mtioc2b/tmci3 sck1/ ssiws0 ts2 cvrefb3 22 p26 cs2# mtioc2a/tmo1 txd1/smosi1/ssda1/ ssirxd0 ts3 cmpb3 23 p25 cs1# mtioc4c/mtclkb/ tioca4 ts4 adtrg0# 24 p24 cs0# mtioc4a/mtclka/tmri1/ tiocb4 usb0_vbusen ts5 25 p23 mtioc3d/mtclkd/ tiocd3 cts0#/rts0#/ss0#/ ssisck0 ts6 26 p22 mtioc3b/mtclkc/tmo0/ tiocc3 sck0/ usb0_ovrcurb/ audio_mclk ts7 27 p21 mtioc1b/tmci0/tioca3 rxd0/smiso0/sscl0/ usb0_exicen/ssiws0 ts8 28 p20 mtioc1a/tmri0/tiocb3 txd0/smosi0/ssda0/ usb0_id/ssirxd0 ts9 29 p17 mtioc3a/mtioc3b/tmo1/ poe8#/tiocb0/tclkd sck1/misoa/sda/ ssitxd0 irq7/ cmpob2 30 p16 mtioc3c/mtioc3d/ tmo2/tiocb1/tclkc/ rtcout txd1/smosi1/ssda1/ mosia/scl/usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6/ adtrg0# 31 p15 mtioc0b/mtclkb/tmci2/ tiocb2/tclkb rxd1/smiso1/sscl1/ crxd0 ts12 irq5/cmpb2 32 p14 mtioc3a/mtclka/tmri2/ tiocb5/tclka cts1#/rts1#/ss1#/ ctxd0/usb0_ovrcura ts13 irq4/ cvrefb2 33 p13 mtioc0b/tmo3/tioca5 sda irq3 34 p12 tmci1 scl irq2 35 vcc_usb* 1 ph3* 1 tmci0* 1 36 ph2* 1 tmri0* 1 usb0_dm* 1 irq1* 1 37 ph1* 1 tmo0* 1 usb0_dp* 1 irq0* 1 38 vss_usb* 1 ph0* 1 cacref* 1 39 p55 wait# mtioc4d/tmo3 crxd0 ts15 40 p54 ale mtioc4b/tmci1 ctxd0 ts16 41 bclk p53 ts17
r01ds0261ej0110 rev.1.10 page 27 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview 42 p52 rd# ts18 43 p51 wr1#/bc1#/ wait# ts19 44 p50 wr0#/wr# ts20 45 ub pc7 a23/cs0# mtioc3a/mtcl kb/tmo2 txd8/smosi8/ssda8/ misoa cacref 46 pc6 a22/cs1# mtioc3c/mtclka/tmci2 rxd8/smiso8/sscl8/ mosia ts22 47 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/tmri2 sck8/rspcka ts23 48 pc4 a20/cs3# mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ ss8#/ssla0 sdhi_d1 tscap 49 pc3 a19 mtioc4d/tclkb txd5/smosi5/ssda5/ irtxd5 sdhi_d0 ts27 50 pc2 a18 mtioc4b/tclka rxd5/smiso5/sscl5/ ssla3/ irrxd5 sdhi_d3 ts30 51 pc1 a17 mtioc3a/tclkd sck5/ssla2 ts33 52 pc0 a16 mtioc3c/tclkc cts5#/rts5#/ss5#/ ssla1 ts35 53 pb7 a15 mtioc3b/tiocb5 txd9/smosi9/ssda9 sdhi_d2 54 pb6 a14 mtioc3d/tioca5 rxd9/smiso9/sscl9 sdhi_d1 55 pb5 a13 mtioc2a/mtioc1b/ tmri1/poe1#/tiocb4 sck9/usb0_vbus sdhi_cd 56 pb4 a12 tioca4 cts9#/rts9#/ss9# 57 pb3 a11 mtioc0a/mtioc4a/tmo0/ poe3#/tiocd3/tclkd sck6 sdhi_w p 58 pb2 a10 tiocc3/tclkc cts6#/rts6#/ss6# 59 pb1 a9 mtioc0c/mtioc4c/ tmci0/tiocb3 txd6/smosi6/ssda6 sdhi_cl k irq4/ cmpob1 60 vcc 61 pb0 a8 mtic5w/tioca3 rxd6/smiso6/sscl6/ rspcka sdhi_c md 62 vss 63 pa7 a7 tiocb2 misoa 64 pa6 a6 mtic5v/mtclkb/tmci3/ poe2#/tioca2 cts5#/rts5#/ss5#/ mosia/ssiws0 65 pa5 a5 tiocb1 rspcka 66 pa4 a4 mtic5u/mtclka/tmri0/ tioca1 txd5/smosi5/ssda5/ ssla0/ssitxd0/irtxd5 irq5 / cvrefb1 67 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb rxd5/smiso5/sscl5/ ssirxd0/irrxd5 irq6 /cmpb1 68 pa2 a2 rxd5/smiso5/sscl5/ ssla3/irrxd5 69 pa1 a1 mtioc0b/mtclkc/ tiocb0 sck5/ssla2/ssisck0 70 pa0 a0/bc0# mtioc4a/tioca0 ssla1 cacref 71 pe7 d15[a15/d15] irq7/an023 72 pe6 d14[a14/d14] irq6/an022 73 pe5 d13[a13/d13] mtioc4c/mtioc2b irq5/an021/ cmpob0 74 pe4 d12[a12/d12] mtioc4d/mtioc1a an020/ cmpa2/ clkout 75 pe3 d11[a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12#/ audio_mclk an019/ clkout 76 pe2 d10[a10/d10] mtioc4a rxd12/rxdx12/ smiso12/sscl12 irq7/an018/ cvrefb0 77 pe1 d9[a9/d9] mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an017/ cmpb0 78 pe0 d8[a8/d8] sck12 an016 table 1.7 list of pins and pin functions (100-pin lfqfp) (2/3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others
r01ds0261ej0110 rev.1.10 page 28 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview note 1. rx230: ph0/cacref, ph1/irq0/tmo0, ph2/irq1/tmri0, ph3/tmci0 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb 79 pd7 d7[a7/d7] mtic5u/poe0# irq7/an031 80 pd6 d6[a6/d6] mtic5v/poe1# irq6/an030 81 pd5 d5[a5/d5] mtic5w/poe2# irq5/an029 82 pd4 d4[a4/d4] poe3# irq4/an028 83 pd3 d3[a3/d3] poe8# irq3/an027 84 pd2 d2[a2/d2] mtioc4d irq2/an026 85 pd1 d1[a1/d1] mtioc4b irq1/an025 86 pd0 d0[a0/d0] irq0/an024 87 p47 an007 88 p46 an006 89 p45 an005 90 p44 an004 91 p43 an003 92 p42 an002 93 p41 an001 94 vrefl0 95 p40 an000 96 vrefh0 97 avcc0 98 p07 adtrg0# 99 avss0 100 p05 da1 table 1.7 list of pins and pin functions (100-pin lfqfp) (3/3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others
r01ds0261ej0110 rev.1.10 page 29 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview table 1.8 list of pins and pin functions (64-pin wflga) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others a1 p05 da1 a2 avcc0 a3 vrefh0 a4 vrefl0 a5 vrefh a6 vrefl a7 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7/an018/ cvrefb0 a8 pe3 mtioc4b/poe8# cts12#/rts12#/ss12#/ audio_mclk an019/clkout b1 vcl b2 avss0 b3 p40 an000 b4 p42 an002 b5 p44 an004 b6 p46 an006 b7 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an017/cmpb0 b8 pe4 mtioc4d/mtioc1a an020/cmpa2/ clkout c1 xcin c2 md fined c3 p03 da0 c4 p41 an001 c5 p43 an003 c6 pe0 sck12 an016 c7 pe5 mtioc4c/mtioc2b irq5/an021/ cmpob0 c8 pa0 mtioc4a/tioca0 ssla1 cacref d1 xcout d2 res# d3 p27 mtioc2b/tmci3 sck1/ ssiws0 ts2 cvrefb3 d4 p14 mtioc3a/mtclka/tmri2/ tiocb5/tclka cts1#/rts1#/ss1#/ctxd0/ usb0_ovrcura ts13 irq4/cvrefb2 d5 pa6 mtic5v/mtclkb/tmci3/poe2#/ tioca2 cts5#/rts5#/ss5#/mosia/ ssiws0 d6 pa4 mtic5u/mtclka/tmri0/tioca1 txd5/smosi5/ssda5/ssla0/ ssitxd0/irtxd5 irq5 /cvrefb1 d7 pa1 mtioc0b/mtclkc/tiocb0 sck5/ssla2/ssisck0 d8 pa3 mtioc0d/mtclkd/tiocd0/ tclkb rxd5/smiso5/sscl5/ssirxd0/ irrxd5 irq6 /cmpb1 e1 vss e2 vbatt e3 p30 mtioc4b/tmri3/poe8#/rtcic0 rxd1/smiso1/sscl1/ audio_mclk irq0/cmpob3 e4 p16 mtioc3c/mtioc3d/tmo2/ tiocb1/tclkc/rtcout txd1/smosi1/ssda1/mosia/ scl/usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6/adtrg0# e5 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 sdhi_d1 tscap e6 vcc e7 vss e8 pb0 mtic5w/tioca3 rxd6/smiso6/sscl6/rspcka sdhi_c md f1 vcc f2 p35 nmi f3 p31 mtioc4d/tmci2/rtcic1 cts1#/rts1#/ss1#/ssisck0 irq1
r01ds0261ej0110 rev.1.10 page 30 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview note 1. rx230: ph0/cacref, ph1/irq0/tmo0, ph2/irq1/tmri0, ph3/tmci0 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb f4 pc5 mtioc3b/mtclkd/tmri 2 sck8/rspcka/usb0_id ts23 f5 p15 mtioc0b/mtclkb/tmci2/ tiocb2/tclkb rxd1/smiso1/sscl1/ crxd0 ts12 irq5/cmpb2 f6 pb1 mtioc0c/mtioc4c/tmci0/ tiocb3 txd6/smosi6/ssda6 sdhi_cl k irq4/ cmpob1 f7 pb5 mtioc2a/mtioc1b/tmri1/ poe1#/tiocb4 sck9 sdhi_cd f8 pb3 mtioc0a/mtioc4a/tmo0/ poe3#/tiocd3/tclkd sck6 sdhi_w p g1 extal p36 g2 p26 mtioc2a/tmo1 txd1/smosi1/ssda1/ usb0_vbusen/ssirxd0 ts3 cmpb3 g3 vcc_usb* 1 ph3* 1 tmci0* 1 g4 vss_usb* 1 ph0* 1 cacref* 1 g5 ub pc7 mtioc3a/mtclkb/tmo2 tx d8/smosi8/ssda8/misoa cacref g6 pc6 mtioc3c/mtclka/tmci2 r xd8/smiso8/sscl8/mosia/ usb0_exicen ts22 g7 pc3 mtioc4d/tclkb txd5/smosi5/ssda5/irtxd5 sdhi_d0 ts27 g8 pb6/pc0 mtioc3d/tioca5 rxd9/smiso9/sscl9 sdhi_d1 h1 xtal p37 h2 p17 mtioc3a/mtioc3b/tmo1/ poe8#/tiocb0/tclkd sck1/misoa/sda/ssitxd0 irq7/ cmpob2 h3 ph2* 1 tmri0* 1 usb0_dm* 1 irq1* 1 h4 ph1* 1 tmo0* 1 usb0_dp* 1 irq0* 1 h5 p55 mtioc4d/tmo3 crxd0 ts15 h6 p54 mtioc4b/tmci1 ctxd0 ts16 h7 pc2 mtioc4b/tclka rxd5/smiso5/sscl5/ssla3/ irrxd5 sdhi_d3 ts30 h8 pb7/pc1 mtioc3b/tiocb5 txd9/smosi9/ssda9 sdhi_d2 table 1.8 list of pins and pin functions (64-pin wflga) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others
r01ds0261ej0110 rev.1.10 page 31 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview table 1.9 list of pins and pin functions (64-pin lqfp/hwqfn) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others 1p 0 3 da0 2vcl 3md fined 4xcin 5 xcout 6 res# 7xtal p37 8 vss 9 extal p36 10 vcc 11 p35 nmi 12 vbatt 13 p31 mtioc4d/tmci2/rtcic1 cts1#/rts1#/ss1#/ssisck0 irq1 14 p30 mtioc4b/tmri3/poe8#/rtcic0 rxd1/smiso1/sscl1/ audio_mclk irq0/cmpob3 15 p27 mtioc2b/tmci3 sck1/ssiws0 ts2 cvrefb3 16 p26 mtioc2a/tmo1 txd1/smosi1/ssda1/ usb0_vbusen/ssirxd0 ts3 cmpb3 17 p17 mtioc3a/mtioc3b/tmo1/ poe8#/tiocb0/tclkd sck1/misoa/sda/ssitxd0 irq7/ cmpob2 18 p16 mtioc3c/mtioc3d/tmo2/ tiocb1/tclkc/rtcout txd1/smosi1/ssda1/mosia/ scl/usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6/adtrg0# 19 p15 mtioc0b/mtclkb/tmci2/ tiocb2/tclkb rxd1/smiso1/sscl1/ crxd0 ts12 irq5/cmpb2 20 p14 mtioc3a/mtclka/tmri2/ tiocb5/tclka cts1#/rts1#/ss1#/ctxd0/ usb0_ovrcura ts13 irq4/cvrefb2 21 vcc_usb* 1 ph3* 1 tmci0* 1 22 ph2* 1 tmri0* 1 usb0_dm* 1 irq1* 1 23 ph1* 1 tmo0* 1 usb0_dp* 1 irq0* 1 24 vss_usb* 1 ph0* 1 cacref* 1 25 p55 mtioc4d/tmo3 crxd0 ts15 26 p54 mtioc4b/tmci1 ctxd0 ts16 27 ub pc7 mtioc3a/mtclkb/tmo2 tx d8/smosi8/ssda8/misoa cacref 28 pc6 mtioc3c/mtclka/tmci2 r xd8/smiso8/sscl8/mosia/ usb0_exicen ts22 29 pc5 mtioc3b/mtclkd/tmri 2 sck8/rspcka/usb0_id ts23 30 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 sdhi_d1 tscap 31 pc3 mtioc4d/tclkb txd5/smosi5/ssda5/ irtxd5 sdhi_d0 ts27 32 pc2 mtioc4b/tclka rxd5/smiso5/sscl5/ssla3/ irrxd5 sdhi_d3 ts30 33 pb7/pc1 mtioc3b/tiocb5 txd9/smosi9/ssda9 sdhi_d2 34 pb6/pc0 mtioc3d/tioca5 rxd9/smiso9/sscl9 sdhi_d1 35 pb5 mtioc2a/mtioc1b/tmri1/ poe1#/tiocb4 sck9 sdhi_cd 36 pb3 mtioc0a/mtioc4a/tmo0/ poe3#/tiocd3/tclkd sck6 sdhi_w p 37 pb1 mtioc0c/mtioc4c/tmci0/ tiocb3 txd6/smosi6/ssda6 sdhi_cl k irq4/ cmpob1 38 vcc 39 pb0 mtic5w/tioca3 rxd6/smiso6/sscl6/rspcka sdhi_c md 40 vss 41 pa6 mtic5v/mtclkb/tmci3/poe2#/ tioca2 cts5#/rts5#/ss5#/mosia/ ssiws0
r01ds0261ej0110 rev.1.10 page 32 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview note 1. rx230: ph0/cacref, ph1/irq0/tmo0, ph2/irq1/tmri0, ph3/tmci0 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb 42 pa4 mtic5u/mtclka/tmri0/tioca1 txd5/smosi5/ssda5/ssla0/ ssitxd0/irtxd5 irq5 /cvrefb1 43 pa3 mtioc0d/mtclkd/tiocd0/ tclkb rxd5/smiso5/sscl5/ssirxd0/ irrxd5 irq6 /cmpb1 44 pa1 mtioc0b/mtclkc/tiocb0 sck5/ssla2/ssisck0 45 pa0 mtioc4a/tioca0 ssla1 cacref 46 pe5 mtioc4c/mtioc2b irq5/an021/ cmpob0 47 pe4 mtioc4d/mtioc1a an020/cmpa2/ clkout 48 pe3 mtioc4b/poe8# cts12#/rts12#/ss12#/ audio_mclk an019/clkout 49 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7/an018/ cvrefb0 50 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an017/cmpb0 51 pe0 sck12 an016 52 vrefl 53 p46 an006 54 vrefh 55 p44 an004 56 p43 an003 57 p42 an002 58 p41 an001 59 vrefl0 60 p40 an000 61 vrefh0 62 avcc0 63 p05 da1 64 avss0 table 1.9 list of pins and pin functions (64-pin lqfp/hwqfn) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others
r01ds0261ej0110 rev.1.10 page 33 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview table 1.10 list of pins and pin functions (48-pin lqfp/hwqfn) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others 1vcl 2md fined 3 res# 4xtal p37 5 vss 6 extal p36 7vcc 8p 3 5 nmi 9 p31 mtioc4d/tmci2 cts1#/rts1#/ss1#/ssisck0 irq1 10 p30 mtioc4b/tmri3/poe8# rxd1/smiso1/sscl1/ audio_mclk irq0/cmpob3 11 p27 mtioc2b/tmci3 sck1/ssiws0 ts2 cvrefb3 12 p26 mtioc2a/tmo1 txd1/smosi1/ssda1/ usb0_vbusen/ssirxd0 ts3 cmpb3 13 p17 mtioc3a/mtioc3b/tmo1/ poe8#/tiocb0/tclkd sck1/misoa/sda/ ssitxd0 irq7/ cmpob2 14 p16 mtioc3c/mtioc3d/tmo2/ tiocb1/tclkc txd1/smosi1/ssda1/mosia/ scl/usb0_vbus/ usb0_vbusen/ usb0_ovrcurb irq6/adtrg0# 15 p15 mtioc0b/mtclkb/tmci2/ tiocb2/tclkb rxd1/smiso1/sscl1/ crxd0 ts12 irq5/cmpb2 16 p14 mtioc3a/mtclka/tmri2/ tiocb5/tclka cts1#/rts1#/ss1#/ctxd0/ usb0_ovrcura ts13 irq4/cvrefb2 17 vcc_usb* 1 ph3* 1 tmci0* 1 18 ph2* 1 tmri0* 1 usb0_dm* 1 irq1* 1 19 ph1* 1 tmo0* 1 usb0_dp* 1 irq0* 1 20 vss_usb* 1 ph0* 1 cacref* 1 21 ub pc7 mtioc3a/mtclkb/tmo2 tx d8/smosi8/ssda8/misoa cacref 22 pc6 mtioc3c/mtclka/tmci2 r xd8/smiso8/sscl8/mosia/ usb0_exicen ts22 23 pc5 mtioc3b/mtclkd/tmri 2 sck8/rspcka/usb0_id ts23 24 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 sdhi_d1 tscap 25 pb5/pc3 mtioc2a/mtioc1b/tmri1/ poe1#/tiocb4 sdhi_cd 26 pb3/pc2 mtioc0a/mtioc4a/tmo0/ poe3#/tiocd3/tclkd sck6 sdhi_w p 27 pb1/pc1 mtioc0c/mtioc4c/tmci0/ tiocb3 txd6/smosi6/ssda6 sdhi_cl k irq4/ cmpob1 28 vcc 29 pb0/pc0 mtic5w/tioca3 rxd6/smiso6/sscl6/rspcka sdhi_c md 30 vss 31 pa6 mtic5v/mtclkb/tmci3/poe2#/ tioca2 cts5#/rts5#/ss5#/mosia/ ssiws0 32 pa4 mtic5u/mtclka/tmri0/tioca1 txd5/smosi5/ssda5/ssla0/ ssitxd0/irtxd5 irq5 /cvrefb1 33 pa3 mtioc0d/mtclkd/tiocd0/ tclkb rxd5/smiso5/sscl5/ssirxd0/ irrxd5 irq6 /cmpb1 34 pa1 mtioc0b/mtclkc/tiocb0 sck5/ssla2/ssisck0 35 pe4 mtioc4d/mtioc1a an020/cmpa2/ clkout 36 pe3 mtioc4b/poe8# cts12#/rts12#/audio_mclk an019/clkout 37 pe2 mtioc4a rxd12/rxdx12/sscl12 irq7/an018/ cvrefb0 38 pe1 mtioc4c txd12/txdx12/siox12/ssda12 an017/cmpb0 39 vrefl 40 p46 an006
r01ds0261ej0110 rev.1.10 page 34 of 177 oct 30, 2015 rx230 group, rx231 group 1. overview note 1. rx230: ph0/cacref, ph1/irq0/tmo0, ph2/irq1/tmri0, ph3/tmci0 rx231: vss_usb, usb0_dp, usb0_dm, vcc_usb 41 vrefh 42 p42 an002 43 p41 an001 44 vrefl0 45 p40 an000 46 vrefh0 47 avcc0 48 avss0 table 1.10 list of pins and pin functions (48-pin lqfp/hwqfn) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, tpu, tmr, rtc, cmt, poe, cac) communications (scig, scih, rspi, riic, can, usb, ssi) memory interface (sdhi) touch sensing others
r01ds0261ej0110 rev.1.10 page 35 of 177 oct 30, 2015 rx230 group, rx231 group 2. cpu 2. cpu figure 2.1 shows register set of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw. r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) *1 general-purpose register b31 b0 dsp instruction register b71 b0 acc0 (accumulator 0) acc1 (accumulator 1) usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) control register b31 b0 extb (exception table register)
r01ds0261ej0110 rev.1.10 page 36 of 177 oct 30, 2015 rx230 group, rx231 group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen 32-bit general-purpose registers (r0 to r15). r0 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by the value of the stack pointer select bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (isp) and user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) exception table register (extb) the exception table register (extb) specifies the address wher e the exception vector table starts. set the extb to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (3) interrupt table register (intb) the interrupt table register (int b) specifies the address where th e interrupt vector table starts. set the intb to a multiple of 4 to reduce the number of cycl es required to execute interr upt sequences and instructions entailing stack manipulation. (4) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (5) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (6) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (7) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (8) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated.
r01ds0261ej0110 rev.1.10 page 37 of 177 oct 30, 2015 rx230 group, rx231 group 2. cpu (9) floating-point st atus word (fpsw) the floating-point status word (fpsw) indicates the results of floating-point operations. when an exception handling enable bit (e j) enables the exception handling (ej = 1) , the exception cause can be identified by checking the corresponding cj flag in the exception handling routine. if th e exception handling is masked (ej = 0), the occurrence of exception can be ch ecked by reading the fj flag at the end of a series of pro cessing. once the fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = x, u, z, o, or v). 2.3 accumulator the accumulator (acc0 or acc1) is a 72-bit register used for dsp instruct ions. the accumulator is handled as a 96-bit register for reading and writing. at this time, when bits 95 to 72 of the accumulator are read , the value where the value of bit 71 is sign extended is read . writing to bits 95 to 72 of the accumulator is ignored. acc0 is also used for the multiply and multiply-and-accumulate in structions; emul, emulu, fmul, mul, and rmpa, in whic h case the prior value in acc0 is modified by execu tion of the instruction. use the mvtacgu, mvtachi, and mvtaclo instructi ons for writing to the accu mulator. the mvtacgu, mvtachi, and mvtaclo instructions write data to bits 95 to 64, the higher-order 32 bits (bits 63 to 32), and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfacgu, mvfa chi, mvfacmi, and mvfaclo in structions for reading data from the accumulator. the mvfacgu, mvfachi, mvfacmi, and mvfaclo instructions r ead data from the guard bits (bits 95 to 64), higher- order 32 bits (bits 63 to 32), the middle 32 bits (bits 47 to 16), and the lower-order 32 bits (bits 31 to 0), respectively.
r01ds0261ej0110 rev.1.10 page 38 of 177 oct 30, 2015 rx230 group, rx231 group 3. address space 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps in the re spective operating modes. accessible areas will differ according to the operating mode and states of control bits.
r01ds0261ej0110 rev.1.10 page 39 of 177 oct 30, 2015 rx230 group, rx231 group 3. address space figure 3.1 memory map in each operating mode reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 external address space (cs area) external address space (cs area) on-chip rom (e2dataflash) reserved area *3 0000 0000h 0008 0000h ffff ffffh single-chip mode* 1 ram *2 on-chip rom (program rom) (read only)* 2 0010 0000h peripheral i/o registers 0010 2000h 0080 0000h fff8 0000h peripheral i/o registers peripheral i/o registers 007f c000h 007f c500h 007f fc00h 0001 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode ram *2 on-chip rom (program rom) (read only)* 2 0010 0000h peripheral i/o registers 0010 2000h on-chip rom (e2dataflash) 0080 0000h 0500 0000h 0800 0000h fff8 0000h peripheral i/o registers peripheral i/o registers 007f c000h 007f c500h 007f fc00h 0001 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode ram *2 0010 0000h peripheral i/o registers 0500 0000h 0800 0000h ff00 0000h 0001 0000h external address space note 1. the address space in boot mode and usb boot mode is the same as the address space in single-chip mode. note 2. the capacity of rom/ram differs depending on the products. note: see table 1.3 and table 1.4 list of products, for the product type name. note 3. reserved areas should not be accessed. rom (bytes) ram (bytes) capacity address capacity address 512 kbytes fff8 0000h to ffff ffffh 64 kbytes 0000 0000h to 0000 ffffh 384 kbytes fffa 0000h to ffff ffffh 256 kbytes fffc 0000h to ffff ffffh 32 kbytes 0000 0000h to 0000 7fffh 128 kbytes fffe 0000h to ffff ffffh
r01ds0261ej0110 rev.1.10 page 40 of 177 oct 30, 2015 rx230 group, rx231 group 3. address space 3.2 external address space the external address space is divided into up to four cs areas (cs0 to cs3) , each corresponding to the csn# signal output from a csn# (n = 0 to 3) pin. figure 3.2 shows the address ranges correspondi ng to the individual cs areas (cs0 to cs3) in on-chip rom disabled extended mode. figure 3.2 correspondence between external address spaces and cs areas (in on-chip rom disabl ed extended mode) reserved area* 1 reserved area* 1 reserved area* 1 0000 0000h 0008 0000h ram external address space (cs area) 0010 0000h peripheral i/o registers 0500 0000h 0800 0000h ff00 0000h 0001 0000h external address space* 2 (cs area) 0500 0000h 0600 0000h 0700 0000h 05ff ffffh 06ff ffffh 07ff ffffh cs3 (16 mbytes) cs2 (16 mbytes) cs1 (16 mbytes) ffff ffffh ffff ffffh ff00 0000h cs0 (16 mbytes) note 1. reserved areas should not be accessed. note 2. the cs0 area is disabled in on-chip rom enabled extended mode. in this mode, the address space for addresses above 1000 0000h is as shown in figure on this section, memory map in each operating mode.
r01ds0261ej0110 rev.1.10 page 41 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 4. i/o registers this section provides information on the on-chip i/o register addresses and bit configuration. the information is given as shown below. notes on writing to registers are also given below. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? numbers of cycles for access indicate numbers of cycles of the given base clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o register , the cpu starts executing the subsequent instru ction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request en able bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0261ej0110 rev.1.10 page 42 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for numbers of clock cycles fo r access to i/o registers, see table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. * 1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral bus 1 to 6 the number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral bus 2 to 6 or registers for the ex ternal bus control unit (except for bus error related registers) are accessed, the number of divided clock synchronization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk, bclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access cycles shown in table 4.1 . when the frequency ratio of iclk is lower than that of pclk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. in the external bus control unit, the sum of the number of bu s cycles for internal main bus 1 and the number of divided clock synchronization cycles will be one cycle of bclk at a maximum. therefore, one bclk is added to the number of access cycles shown in table 4.1 . note 1. this applies to the number of cycles when the access fr om the cpu does not conflict with the instruction fetching to the external memory or bus access from the different bus master (dmac or dtc). (4) restrictions in relation to rmpa and string-manipulation instructions the allocation of data to be handled by rmpa or string-man ipulation instructions to i/o registers is prohibited, and operation is not guaranteed if this restriction is not observed. (5) notes on sleep mode and mode transitions during sleep mode or mode transitions, do not write to the sy stem control related registers (indicated by 'system' in the module symbol column in table 4.1, list of i/o registers (address order) ).
r01ds0261ej0110 rev.1.10 page 43 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o register s (address order) (1 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 44 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2000h dmac0 dma source address register dmsar 32 32 2 iclk 0008 2004h dmac0 dma destination address register dmdar 32 32 2 iclk 0008 2008h dmac0 dma transfer count register dmcra 32 32 2 iclk 0008 200ch dmac0 dma block transfer count register dmcrb 16 16 2 iclk 0008 2010h dmac0 dma transfer mode register dmtmd 16 16 2 iclk 0008 2013h dmac0 dma interrupt setting register dmint 8 8 2 iclk 0008 2014h dmac0 dma address mode register dmamd 16 16 2 iclk 0008 2018h dmac0 dma offset register dmofr 32 32 2 iclk 0008 201ch dmac0 dma transfer enable register dmcnt 8 8 2 iclk 0008 201dh dmac0 dma software start register dmreq 8 8 2 iclk 0008 201eh dmac0 dma status register dmsts 8 8 2 iclk 0008 201fh dmac0 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2040h dmac1 dma source address register dmsar 32 32 2 iclk 0008 2044h dmac1 dma destination address register dmdar 32 32 2 iclk 0008 2048h dmac1 dma transfer count register dmcra 32 32 2 iclk 0008 204ch dmac1 dma block transfer count register dmcrb 16 16 2 iclk 0008 2050h dmac1 dma transfer mode register dmtmd 16 16 2 iclk 0008 2053h dmac1 dma interrupt setting register dmint 8 8 2 iclk 0008 2054h dmac1 dma address mode register dmamd 16 16 2 iclk 0008 205ch dmac1 dma transfer enable register dmcnt 8 8 2 iclk 0008 205dh dmac1 dma software start register dmreq 8 8 2 iclk 0008 205eh dmac1 dma status register dmsts 8 8 2 iclk 0008 205fh dmac1 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2080h dmac2 dma source address register dmsar 32 32 2 iclk 0008 2084h dmac2 dma destination address register dmdar 32 32 2 iclk 0008 2088h dmac2 dma transfer count register dmcra 32 32 2 iclk 0008 208ch dmac2 dma block transfer count register dmcrb 16 16 2 iclk 0008 2090h dmac2 dma transfer mode register dmtmd 16 16 2 iclk 0008 2093h dmac2 dma interrupt setting register dmint 8 8 2 iclk 0008 2094h dmac2 dma address mode register dmamd 16 16 2 iclk 0008 209ch dmac2 dma transfer enable register dmcnt 8 8 2 iclk 0008 209dh dmac2 dma software start register dmreq 8 8 2 iclk 0008 209eh dmac2 dma status register dmsts 8 8 2 iclk 0008 209fh dmac2 dma activation source flag control register dmcsl 8 8 2 iclk 0008 20c0h dmac3 dma source address register dmsar 32 32 2 iclk 0008 20c4h dmac3 dma destination address register dmdar 32 32 2 iclk 0008 20c8h dmac3 dma transfer count register dmcra 32 32 2 iclk 0008 20cch dmac3 dma block transfer count register dmcrb 16 16 2 iclk 0008 20d0h dmac3 dma transfer mode register dmtmd 16 16 2 iclk 0008 20d3h dmac3 dma interrupt setting register dmint 8 8 2 iclk 0008 20d4h dmac3 dma address mode register dmamd 16 16 2 iclk 0008 20dch dmac3 dma transfer enable register dmcnt 8 8 2 iclk 0008 20ddh dmac3 dma software start register dmreq 8 8 2 iclk 0008 20deh dmac3 dma status register dmsts 8 8 2 iclk 0008 20dfh dmac3 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2200h dmac dma module activation register dmast 8 8 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk table 4.1 list of i/o register s (address order) (2 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 45 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk 0008 3002h bsc cs0 mode register cs0mod 16 16 1 or 2 bclk 0008 3004h bsc cs0 wait control register 1 cs0wcr1 32 32 1 or 2 bclk 0008 3008h bsc cs0 wait control register 2 cs0wcr2 32 32 1 or 2 bclk 0008 3012h bsc cs1 mode register cs1mod 16 16 1 or 2 bclk 0008 3014h bsc cs1 wait control register 1 cs1wcr1 32 32 1 or 2 bclk 0008 3018h bsc cs1 wait control register 2 cs1wcr2 32 32 1 or 2 bclk 0008 3022h bsc cs2 mode register cs2mod 16 16 1 or 2 bclk 0008 3024h bsc cs2 wait control register 1 cs2wcr1 32 32 1 or 2 bclk 0008 3028h bsc cs2 wait control register 2 cs2wcr2 32 32 1 or 2 bclk 0008 3032h bsc cs3 mode register cs3mod 16 16 1 or 2 bclk 0008 3034h bsc cs3 wait control register 1 cs3wcr1 32 32 1 or 2 bclk 0008 3038h bsc cs3 wait control register 2 cs3wcr2 32 32 1 or 2 bclk 0008 3802h bsc cs0 control register cs0cr 16 16 1 or 2 bclk 0008 380ah bsc cs0 recovery cycle register cs0rec 16 16 1 or 2 bclk 0008 3812h bsc cs1 control register cs1cr 16 16 1 or 2 bclk 0008 381ah bsc cs1 recovery cycle register cs1rec 16 16 1 or 2 bclk 0008 3822h bsc cs2 control register cs2cr 16 16 1 or 2 bclk 0008 382ah bsc cs2 recovery cycle register cs2rec 16 16 1 or 2 bclk 0008 3832h bsc cs3 control register cs3cr 16 16 1 or 2 bclk 0008 383ah bsc cs3 recovery cycle register cs3rec 16 16 1 or 2 bclk 0008 3880h bsc cs recovery cycle insertion enable register csrecen 16 16 1 or 2 bclk 0008 6400h mpu region-0 start page number register rspage0 32 32 1 iclk 0008 6404h mpu region-0 end page number register repage0 32 32 1 iclk 0008 6408h mpu region-1 start page number register rspage1 32 32 1 iclk 0008 640ch mpu region-1 end page number register repage1 32 32 1 iclk 0008 6410h mpu region-2 start page number register rspage2 32 32 1 iclk 0008 6414h mpu region-2 end page number register repage2 32 32 1 iclk 0008 6418h mpu region-3 start page number register rspage3 32 32 1 iclk 0008 641ch mpu region-3 end page number register repage3 32 32 1 iclk 0008 6420h mpu region-4 start page number register rspage4 32 32 1 iclk 0008 6424h mpu region-4 end page number register repage4 32 32 1 iclk 0008 6428h mpu region-5 start page number register rspage5 32 32 1 iclk 0008 642ch mpu region-5 end page number register repage5 32 32 1 iclk 0008 6430h mpu region-6 start page number register rspage6 32 32 1 iclk 0008 6434h mpu region-6 end page number register repage6 32 32 1 iclk 0008 6438h mpu region-7 start page number register rspage7 32 32 1 iclk 0008 643ch mpu region-7 end page number register repage7 32 32 1 iclk 0008 6500h mpu memory-protection enable register mpen 32 32 1 iclk 0008 6504h mpu background access control register mpbac 32 32 1 iclk 0008 6508h mpu memory-protection error status-clearing register mpeclr 32 32 1 iclk 0008 650ch mpu memory-protection error status register mpests 32 32 1 iclk 0008 6514h mpu data memory-protection error address register mpdea 32 32 1 iclk 0008 6520h mpu region search address register mpsa 32 32 1 iclk 0008 6524h mpu region search operation register mpops 16 16 1 iclk 0008 6526h mpu region invalidation operation register mpopi 16 16 1 iclk 0008 6528h mpu instruction-hit region register mhiti 32 32 1 iclk 0008 652ch mpu data-hit region register mhitd 32 32 1 iclk 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk table 4.1 list of i/o register s (address order) (3 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 46 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk 0008 7023h icu interrupt request register 035 ir035 8 8 2 iclk 0008 7025h icu interrupt request register 037 ir037 8 8 2 iclk 0008 7026h icu interrupt request register 038 ir038 8 8 2 iclk 0008 7028h icu interrupt request register 040 ir040 8 8 2 iclk 0008 7029h icu interrupt request register 041 ir041 8 8 2 iclk 0008 702ah icu interrupt request register 042 ir042 8 8 2 iclk 0008 702bh icu interrupt request register 043 ir043 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7030h icu interrupt request register 048 ir048 8 8 2 iclk 0008 7031h icu interrupt request register 049 ir049 8 8 2 iclk 0008 7032h icu interrupt request register 050 ir050 8 8 2 iclk 0008 7033h icu interrupt request register 051 ir051 8 8 2 iclk 0008 7034h icu interrupt request register 052 ir052 8 8 2 iclk 0008 7035h icu interrupt request register 053 ir053 8 8 2 iclk 0008 7036h icu interrupt request register 054 ir054 8 8 2 iclk 0008 7037h icu interrupt request register 055 ir055 8 8 2 iclk 0008 7038h icu interrupt request register 056 ir056 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 703ah icu interrupt request register 058 ir058 8 8 2 iclk 0008 703bh icu interrupt request register 059 ir059 8 8 2 iclk 0008 703ch icu interrupt request register 060 ir060 8 8 2 iclk 0008 703dh icu interrupt request register 061 ir061 8 8 2 iclk 0008 703eh icu interrupt request register 062 ir062 8 8 2 iclk 0008 703fh icu interrupt request register 063 ir063 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7051h icu interrupt request register 081 ir081 8 8 2 iclk 0008 7058h icu interrupt request register 088 ir088 8 8 2 iclk 0008 7059h icu interrupt request register 089 ir089 8 8 2 iclk 0008 705ah icu interrupt request register 090 ir090 8 8 2 iclk 0008 705bh icu interrupt request register 091 ir091 8 8 2 iclk 0008 705ch icu interrupt request register 092 ir092 8 8 2 iclk 0008 705dh icu interrupt request register 093 ir093 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 7068h icu interrupt request register 104 ir104 8 8 2 iclk table 4.1 list of i/o register s (address order) (4 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 47 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 7069h icu interrupt request register 105 ir105 8 8 2 iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk 0008 706bh icu interrupt request register 107 ir107 8 8 2 iclk 0008 706ch icu interrupt request register 108 ir108 8 8 2 iclk 0008 706dh icu interrupt request register 109 ir109 8 8 2 iclk 0008 706eh icu interrupt request register 110 ir110 8 8 2 iclk 0008 706fh icu interrupt request register 111 ir111 8 8 2 iclk 0008 7070h icu interrupt request register 112 ir112 8 8 2 iclk 0008 7071h icu interrupt request register 113 ir113 8 8 2 iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 708eh icu interrupt request register 142 ir142 8 8 2 iclk 0008 708fh icu interrupt request register 143 ir143 8 8 2 iclk 0008 7090h icu interrupt request register 144 ir144 8 8 2 iclk 0008 7091h icu interrupt request register 145 ir145 8 8 2 iclk 0008 7092h icu interrupt request register 146 ir146 8 8 2 iclk 0008 7093h icu interrupt request register 147 ir147 8 8 2 iclk 0008 7094h icu interrupt request register 148 ir148 8 8 2 iclk 0008 7095h icu interrupt request register 149 ir149 8 8 2 iclk 0008 7096h icu interrupt request register 150 ir150 8 8 2 iclk 0008 7097h icu interrupt request register 151 ir151 8 8 2 iclk 0008 7098h icu interrupt request register 152 ir152 8 8 2 iclk 0008 7099h icu interrupt request register 153 ir153 8 8 2 iclk 0008 709ah icu interrupt request register 154 ir154 8 8 2 iclk 0008 709bh icu interrupt request register 155 ir155 8 8 2 iclk 0008 709ch icu interrupt request register 156 ir156 8 8 2 iclk table 4.1 list of i/o register s (address order) (5 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 48 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 709dh icu interrupt request register 157 ir157 8 8 2 iclk 0008 709eh icu interrupt request register 158 ir158 8 8 2 iclk 0008 709fh icu interrupt request register 159 ir159 8 8 2 iclk 0008 70a0h icu interrupt request register 160 ir160 8 8 2 iclk 0008 70a1h icu interrupt request register 161 ir161 8 8 2 iclk 0008 70a2h icu interrupt request register 162 ir162 8 8 2 iclk 0008 70a3h icu interrupt request register 163 ir163 8 8 2 iclk 0008 70a4h icu interrupt request register 164 ir164 8 8 2 iclk 0008 70a5h icu interrupt request register 165 ir165 8 8 2 iclk 0008 70a6h icu interrupt request register 166 ir166 8 8 2 iclk 0008 70a7h icu interrupt request register 167 ir167 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70c6h icu interrupt request register 198 ir198 8 8 2 iclk 0008 70c7h icu interrupt request register 199 ir199 8 8 2 iclk 0008 70c8h icu interrupt request register 200 ir200 8 8 2 iclk 0008 70c9h icu interrupt request register 201 ir201 8 8 2 iclk 0008 70d6h icu interrupt request register 214 ir214 8 8 2 iclk 0008 70d7h icu interrupt request register 215 ir215 8 8 2 iclk 0008 70d8h icu interrupt request register 216 ir216 8 8 2 iclk 0008 70d9h icu interrupt request register 217 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70e6h icu interrupt request register 230 ir230 8 8 2 iclk 0008 70e7h icu interrupt request register 231 ir231 8 8 2 iclk 0008 70e8h icu interrupt request register 232 ir232 8 8 2 iclk 0008 70e9h icu interrupt request register 233 ir233 8 8 2 iclk 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk table 4.1 list of i/o register s (address order) (6 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 49 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 70edh icu interrupt request register 237 ir237 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f2h icu interrupt request register 242 ir242 8 8 2 iclk 0008 70f3h icu interrupt request register 243 ir243 8 8 2 iclk 0008 70f4h icu interrupt request register 244 ir244 8 8 2 iclk 0008 70f5h icu interrupt request register 245 ir245 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 70fah icu interrupt request register 250 ir250 8 8 2 iclk 0008 70fbh icu interrupt request register 251 ir251 8 8 2 iclk 0008 70fch icu interrupt request register 252 ir252 8 8 2 iclk 0008 70fdh icu interrupt request register 253 ir253 8 8 2 iclk 0008 70feh icu interrupt request register 254 ir254 8 8 2 iclk 0008 70ffh icu interrupt request register 255 ir255 8 8 2 iclk 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2 iclk 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2 iclk 0008 7124h icu dtc activation enable register 036 dtcer036 8 8 2 iclk 0008 7125h icu dtc activation enable register 037 dtcer037 8 8 2 iclk 0008 7128h icu dtc activation enable register 040 dtcer040 8 8 2 iclk 0008 712dh icu dtc activation enable register 045 dtcer045 8 8 2 iclk 0008 712eh icu dtc activation enable register 046 dtcer046 8 8 2 iclk 0008 7134h icu dtc activation enable register 052 dtcer052 8 8 2 iclk 0008 713ah icu dtc activation enable register 058 dtcer058 8 8 2 iclk 0008 713bh icu dtc activation enable register 059 dtcer059 8 8 2 iclk 0008 713ch icu dtc activation enable register 060 dtcer060 8 8 2 iclk 0008 713dh icu dtc activation enable register 061 dtcer061 8 8 2 iclk 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2 iclk 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2 iclk 0008 7146h icu dtc activation enable register 070 dtcer070 8 8 2 iclk 0008 7147h icu dtc activation enable register 071 dtcer071 8 8 2 iclk 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2 iclk 0008 7167h icu dtc activation enable register 103 dtcer103 8 8 2 iclk 0008 7168h icu dtc activation enable register 104 dtcer104 8 8 2 iclk 0008 7169h icu dtc activation enable register 105 dtcer105 8 8 2 iclk 0008 716ah icu dtc activation enable register 106 dtcer106 8 8 2 iclk 0008 716bh icu dtc activation enable register 107 dtcer107 8 8 2 iclk 0008 716dh icu dtc activation enable register 109 dtcer109 8 8 2 iclk 0008 716eh icu dtc activation enable register 110 dtcer110 8 8 2 iclk 0008 716fh icu dtc activation enable register 111 dtcer111 8 8 2 iclk 0008 7170h icu dtc activation enable register 112 dtcer112 8 8 2 iclk table 4.1 list of i/o register s (address order) (7 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 50 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 7172h icu dtc activation enable register 114 dtcer114 8 8 2 iclk 0008 7173h icu dtc activation enable register 115 dtcer115 8 8 2 iclk 0008 7174h icu dtc activation enable register 116 dtcer116 8 8 2 iclk 0008 7175h icu dtc activation enable register 117 dtcer117 8 8 2 iclk 0008 7179h icu dtc activation enable register 121 dtcer121 8 8 2 iclk 0008 717ah icu dtc activation enable register 122 dtcer122 8 8 2 iclk 0008 717dh icu dtc activation enable register 125 dtcer125 8 8 2 iclk 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2 iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2 iclk 0008 7182h icu dtc activation enable register 130 dtcer130 8 8 2 iclk 0008 7183h icu dtc activation enable register 131 dtcer131 8 8 2 iclk 0008 7184h icu dtc activation enable register 132 dtcer132 8 8 2 iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2 iclk 0008 7187h icu dtc activation enable register 135 dtcer135 8 8 2 iclk 0008 7188h icu dtc activation enable register 136 dtcer136 8 8 2 iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2 iclk 0008 718bh icu dtc activation enable register 139 dtcer139 8 8 2 iclk 0008 718ch icu dtc activation enable register 140 dtcer140 8 8 2 iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2 iclk 0008 718eh icu dtc activation enable register 142 dtcer142 8 8 2 iclk 0008 7193h icu dtc activation enable register 147 dtcer147 8 8 2 iclk 0008 7194h icu dtc activation enable register 148 dtcer148 8 8 2 iclk 0008 7197h icu dtc activation enable register 151 dtcer151 8 8 2 iclk 0008 7198h icu dtc activation enable register 152 dtcer152 8 8 2 iclk 0008 719bh icu dtc activation enable register 155 dtcer155 8 8 2 iclk 0008 719ch icu dtc activation enable register 156 dtcer156 8 8 2 iclk 0008 719dh icu dtc activation enable register 157 dtcer157 8 8 2 iclk 0008 719eh icu dtc activation enable register 158 dtcer158 8 8 2 iclk 0008 71a0h icu dtc activation enable register 160 dtcer160 8 8 2 iclk 0008 71a1h icu dtc activation enable register 161 dtcer161 8 8 2 iclk 0008 71a4h icu dtc activation enable register 164 dtcer164 8 8 2 iclk 0008 71a5h icu dtc activation enable register 165 dtcer165 8 8 2 iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2 iclk 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2 iclk 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2 iclk 0008 71c6h icu dtc activation enable register 198 dtcer198 8 8 2 iclk 0008 71c7h icu dtc activation enable register 199 dtcer199 8 8 2 iclk 0008 71c8h icu dtc activation enable register 200 dtcer200 8 8 2 iclk 0008 71c9h icu dtc activation enable register 201 dtcer201 8 8 2 iclk 0008 71d7h icu dtc activation enable register 215 dtcer215 8 8 2 iclk 0008 71d8h icu dtc activation enable register 216 dtcer216 8 8 2 iclk 0008 71dbh icu dtc activation enable register 219 dtcer219 8 8 2 iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2 iclk 0008 71e3h icu dtc activation enable register 227 dtcer227 8 8 2 iclk table 4.1 list of i/o register s (address order) (8 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 51 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 71e4h icu dtc activation enable register 228 dtcer228 8 8 2 iclk 0008 71e7h icu dtc activation enable register 231 dtcer231 8 8 2 iclk 0008 71e8h icu dtc activation enable register 232 dtcer232 8 8 2 iclk 0008 71ebh icu dtc activation enable register 235 dtcer235 8 8 2 iclk 0008 71ech icu dtc activation enable register 236 dtcer236 8 8 2 iclk 0008 71efh icu dtc activation enable register 239 dtcer239 8 8 2 iclk 0008 71f0h icu dtc activation enable register 240 dtcer240 8 8 2 iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2 iclk 0008 71fbh icu dtc activation enable register 251 dtcer251 8 8 2 iclk 0008 71fch icu dtc activation enable register 252 dtcer252 8 8 2 iclk 0008 71fdh icu dtc activation enable register 253 dtcer253 8 8 2 iclk 0008 71feh icu dtc activation enable register 254 dtcer254 8 8 2 iclk 0008 71ffh icu dtc activation enable register 255 dtcer255 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7206h icu interrupt request enable register 06 ier06 8 8 2 iclk 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 720ah icu interrupt request enable register 0a ier0a 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7212h icu interrupt request enable register 12 ier12 8 8 2 iclk 0008 7213h icu interrupt request enable register 13 ier13 8 8 2 iclk 0008 7214h icu interrupt request enable register 14 ier14 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19 ier19 8 8 2 iclk 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 2 iclk 0008 7302h icu interrupt source priority register 002 ipr002 8 8 2 iclk 0008 7303h icu interrupt source priority register 003 ipr003 8 8 2 iclk 0008 7304h icu interrupt source priority register 004 ipr004 8 8 2 iclk 0008 7305h icu interrupt source priority register 005 ipr005 8 8 2 iclk 0008 7306h icu interrupt source priority register 006 ipr006 8 8 2 iclk 0008 7307h icu interrupt source priority register 007 ipr007 8 8 2 iclk table 4.1 list of i/o register s (address order) (9 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 52 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 7320h icu interrupt source priority register 032 ipr032 8 8 2 iclk 0008 7321h icu interrupt source priority register 033 ipr033 8 8 2 iclk 0008 7322h icu interrupt source priority register 034 ipr034 8 8 2 iclk 0008 7324h icu interrupt source priority register 036 ipr036 8 8 2 iclk 0008 7325h icu interrupt source priority register 037 ipr037 8 8 2 iclk 0008 7326h icu interrupt source priority register 038 ipr038 8 8 2 iclk 0008 7328h icu interrupt source priority register 040 ipr040 8 8 2 iclk 0008 7329h icu interrupt source priority register 041 ipr041 8 8 2 iclk 0008 732ah icu interrupt source priority register 042 ipr042 8 8 2 iclk 0008 732bh icu interrupt source priority register 043 ipr043 8 8 2 iclk 0008 732ch icu interrupt source priority register 044 ipr044 8 8 2 iclk 0008 7334h icu interrupt source priority register 052 ipr052 8 8 2 iclk 0008 7335h icu interrupt source priority register 053 ipr053 8 8 2 iclk 0008 7336h icu interrupt source priority register 054 ipr054 8 8 2 iclk 0008 7337h icu interrupt source priority register 055 ipr055 8 8 2 iclk 0008 7338h icu interrupt source priority register 056 ipr056 8 8 2 iclk 0008 7339h icu interrupt source priority register 057 ipr057 8 8 2 iclk 0008 733ah icu interrupt source priority register 058 ipr058 8 8 2 iclk 0008 733bh icu interrupt source priority register 059 ipr059 8 8 2 iclk 0008 733ch icu interrupt source priority register 060 ipr060 8 8 2 iclk 0008 733fh icu interrupt source priority register 063 ipr063 8 8 2 iclk 0008 7340h icu interrupt source priority register 064 ipr064 8 8 2 iclk 0008 7341h icu interrupt source priority register 065 ipr065 8 8 2 iclk 0008 7342h icu interrupt source priority register 066 ipr066 8 8 2 iclk 0008 7343h icu interrupt source priority register 067 ipr067 8 8 2 iclk 0008 7344h icu interrupt source priority register 068 ipr068 8 8 2 iclk 0008 7345h icu interrupt source priority register 069 ipr069 8 8 2 iclk 0008 7346h icu interrupt source priority register 070 ipr070 8 8 2 iclk 0008 7347h icu interrupt source priority register 071 ipr071 8 8 2 iclk 0008 7350h icu interrupt source priority register 080 ipr080 8 8 2 iclk 0008 7358h icu interrupt source priority register 088 ipr088 8 8 2 iclk 0008 7359h icu interrupt source priority register 089 ipr089 8 8 2 iclk 0008 735ch icu interrupt source priority register 092 ipr092 8 8 2 iclk 0008 735dh icu interrupt source priority register 093 ipr093 8 8 2 iclk 0008 7366h icu interrupt source priority register 102 ipr102 8 8 2 iclk 0008 7367h icu interrupt source priority register 103 ipr103 8 8 2 iclk 0008 7368h icu interrupt source priority register 104 ipr104 8 8 2 iclk 0008 7369h icu interrupt source priority register 105 ipr105 8 8 2 iclk 0008 736ah icu interrupt source priority register 106 ipr106 8 8 2 iclk 0008 736bh icu interrupt source priority register 107 ipr107 8 8 2 iclk 0008 736ch icu interrupt source priority register 108 ipr108 8 8 2 iclk 0008 736fh icu interrupt source priority register 111 ipr111 8 8 2 iclk 0008 7371h icu interrupt source priority register 113 ipr113 8 8 2 iclk 0008 7372h icu interrupt source priority register 114 ipr114 8 8 2 iclk 0008 7376h icu interrupt source priority register 118 ipr118 8 8 2 iclk 0008 7379h icu interrupt source priority register 121 ipr121 8 8 2 iclk 0008 737bh icu interrupt source priority register 123 ipr123 8 8 2 iclk 0008 737dh icu interrupt source priority register 125 ipr125 8 8 2 iclk 0008 737fh icu interrupt source priority register 127 ipr127 8 8 2 iclk 0008 7381h icu interrupt source priority register 129 ipr129 8 8 2 iclk 0008 7385h icu interrupt source priority register 133 ipr133 8 8 2 iclk 0008 7386h icu interrupt source priority register 134 ipr134 8 8 2 iclk table 4.1 list of i/o register s (address order) (10 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 53 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 738ah icu interrupt source priority register 138 ipr138 8 8 2 iclk 0008 738bh icu interrupt source priority register 139 ipr139 8 8 2 iclk 0008 738eh icu interrupt source priority register 142 ipr142 8 8 2 iclk 0008 7392h icu interrupt source priority register 146 ipr146 8 8 2 iclk 0008 7393h icu interrupt source priority register 147 ipr147 8 8 2 iclk 0008 7395h icu interrupt source priority register 149 ipr149 8 8 2 iclk 0008 7397h icu interrupt source priority register 151 ipr151 8 8 2 iclk 0008 7399h icu interrupt source priority register 153 ipr153 8 8 2 iclk 0008 739bh icu interrupt source priority register 155 ipr155 8 8 2 iclk 0008 739fh icu interrupt source priority register 159 ipr159 8 8 2 iclk 0008 73a0h icu interrupt source priority register 160 ipr160 8 8 2 iclk 0008 73a2h icu interrupt source priority register 162 ipr162 8 8 2 iclk 0008 73a4h icu interrupt source priority register 164 ipr164 8 8 2 iclk 0008 73a6h icu interrupt source priority register 166 ipr166 8 8 2 iclk 0008 73aah icu interrupt source priority register 170 ipr170 8 8 2 iclk 0008 73abh icu interrupt source priority register 171 ipr171 8 8 2 iclk 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 2 iclk 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 2 iclk 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 2 iclk 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 2 iclk 0008 73c6h icu interrupt source priority register 198 ipr198 8 8 2 iclk 0008 73c7h icu interrupt source priority register 199 ipr199 8 8 2 iclk 0008 73c8h icu interrupt source priority register 200 ipr200 8 8 2 iclk 0008 73c9h icu interrupt source priority register 201 ipr201 8 8 2 iclk 0008 73d6h icu interrupt source priority register 214 ipr214 8 8 2 iclk 0008 73dah icu interrupt source priority register 218 ipr218 8 8 2 iclk 0008 73deh icu interrupt source priority register 222 ipr222 8 8 2 iclk 0008 73e2h icu interrupt source priority register 226 ipr226 8 8 2 iclk 0008 73e6h icu interrupt source priority register 230 ipr230 8 8 2 iclk 0008 73eah icu interrupt source priority register 234 ipr234 8 8 2 iclk 0008 73eeh icu interrupt source priority register 238 ipr238 8 8 2 iclk 0008 73f2h icu interrupt source priority register 242 ipr242 8 8 2 iclk 0008 73f3h icu interrupt source priority register 243 ipr243 8 8 2 iclk 0008 73f4h icu interrupt source priority register 244 ipr244 8 8 2 iclk 0008 73f5h icu interrupt source priority register 245 ipr245 8 8 2 iclk 0008 73f6h icu interrupt source priority register 246 ipr246 8 8 2 iclk 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 2 iclk 0008 73f8h icu interrupt source priority register 248 ipr248 8 8 2 iclk 0008 73f9h icu interrupt source priority register 249 ipr249 8 8 2 iclk 0008 73fah icu interrupt source priority register 250 ipr250 8 8 2 iclk 0008 73fbh icu interrupt source priority register 251 ipr251 8 8 2 iclk 0008 73fch icu interrupt source priority register 252 ipr252 8 8 2 iclk 0008 73fdh icu interrupt source priority register 253 ipr253 8 8 2 iclk 0008 73feh icu interrupt source priority register 254 ipr254 8 8 2 iclk 0008 73ffh icu interrupt source priority register 255 ipr255 8 8 2 iclk 0008 7400h icu dmac activation request select register 0 dmrsr0 8 8 2 iclk 0008 7404h icu dmac activation request select register 1 dmrsr1 8 8 2 iclk 0008 7408h icu dmac activation request select register 2 dmrsr2 8 8 2 iclk 0008 740ch icu dmac activation request select register 3 dmrsr3 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk table 4.1 list of i/o register s (address order) (11 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 54 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt status clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2 or 3 pclkb 2 iclk 0008 8002h cmt0 compare match timer control register cmcr 16 16 2 or 3 pclkb 2 iclk 0008 8004h cmt0 compare match counter cmcnt 16 16 2 or 3 pclkb 2 iclk 0008 8006h cmt0 compare match constant register cmcor 16 16 2 or 3 pclkb 2 iclk 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 or 3 pclkb 2 iclk 0008 800ah cmt1 compare match counter cmcnt 16 16 2 or 3 pclkb 2 iclk 0008 800ch cmt1 compare match constant register cmcor 16 16 2 or 3 pclkb 2 iclk 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2 or 3 pclkb 2 iclk 0008 8012h cmt2 compare match timer control register cmcr 16 16 2 or 3 pclkb 2 iclk 0008 8014h cmt2 compare match counter cmcnt 16 16 2 or 3 pclkb 2 iclk 0008 8016h cmt2 compare match constant register cmcor 16 16 2 or 3 pclkb 2 iclk 0008 8018h cmt3 compare match timer control register cmcr 16 16 2 or 3 pclkb 2 iclk 0008 801ah cmt3 compare match counter cmcnt 16 16 2 or 3 pclkb 2 iclk 0008 801ch cmt3 compare match constant register cmcor 16 16 2 or 3 pclkb 2 iclk 0008 8020h wdt wdt refresh register wdtrr 8 8 2 or 3 pclkb 2 iclk 0008 8022h wdt wdt control register wdtcr 16 16 2 or 3 pclkb 2 iclk 0008 8024h wdt wdt status register wdtsr 16 16 2 or 3 pclkb 2 iclk 0008 8026h wdt wdt reset control register wdtrcr 8 8 2 or 3 pclkb 2 iclk 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2 or 3 pclkb 2 iclk 0008 8032h iwdt iwdt control register iwdtcr 16 16 2 or 3 pclkb 2 iclk 0008 8034h iwdt iwdt status register iwdtsr 16 16 2 or 3 pclkb 2 iclk 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2 or 3 pclkb 2 iclk 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2 or 3 pclkb 2 iclk 0008 8040h da d/a data register 0 dadr0 16 16 2 or 3 pclkb 2 iclk 0008 8042h da d/a data register 1 dadr1 16 16 2 or 3 pclkb 2 iclk 0008 8044h da d/a control register dacr 8 8 2 or 3 pclkb 2 iclk 0008 8045h da dadrm format select register dadpr 8 8 2 or 3 pclkb 2 iclk 0008 8046h da d/a a/d synchronous start control register daadscr 8 8 2 or 3 pclkb 2 iclk 0008 8047h da d/a vref control register davrefcr 8 8 2 or 3 pclkb 2 iclk 0008 8100h tpu timer start register tstr 8 8 2 or 3 pclkb 2 iclk 0008 8101h tpu timer synchronous register tsyr 8 8 2 or 3 pclkb 2 iclk 0008 8108h tpu0 noise filter control register nfcr 8 8 2 or 3 pclkb 2 iclk 0008 8109h tpu1 noise filter control register nfcr 8 8 2 or 3 pclkb 2 iclk 0008 810ah tpu2 noise filter control register nfcr 8 8 2 or 3 pclkb 2 iclk 0008 810bh tpu3 noise filter control register nfcr 8 8 2 or 3 pclkb 2 iclk 0008 810ch tpu4 noise filter control register nfcr 8 8 2 or 3 pclkb 2 iclk 0008 810dh tpu5 noise filter control register nfcr 8 8 2 or 3 pclkb 2 iclk 0008 8110h tpu0 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8111h tpu0 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (12 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 55 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 8112h tpu0 timer i/o control register h tiorh 8 8 2 or 3 pclkb 2 iclk 0008 8113h tpu0 timer i/o control register l tiorl 8 8 2 or 3 pclkb 2 iclk 0008 8114h tpu0 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 0008 8115h tpu0 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 0008 8116h tpu0 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 0008 8118h tpu0 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 0008 811ah tpu0 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 0008 811ch tpu0 timer general register c tgrc 16 16 2 or 3 pclkb 2 iclk 0008 811eh tpu0 timer general register d tgrd 16 16 2 or 3 pclkb 2 iclk 0008 8120h tpu1 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8121h tpu1 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 0008 8122h tpu1 timer i/o control register tior 8 8 2 or 3 pclkb 2 iclk 0008 8124h tpu1 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 0008 8125h tpu1 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 0008 8126h tpu1 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 0008 8128h tpu1 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 0008 812ah tpu1 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 0008 8130h tpu2 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8131h tpu2 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 0008 8132h tpu2 timer i/o control register tior 8 8 2 or 3 pclkb 2 iclk 0008 8134h tpu2 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 0008 8135h tpu2 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 0008 8136h tpu2 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 0008 8138h tpu2 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 0008 813ah tpu2 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 0008 8140h tpu3 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8141h tpu3 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 0008 8142h tpu3 timer i/o control register h tiorh 8 8 2 or 3 pclkb 2 iclk 0008 8143h tpu3 timer i/o control register l tiorl 8 8 2 or 3 pclkb 2 iclk 0008 8144h tpu3 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 0008 8145h tpu3 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 0008 8146h tpu3 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 0008 8148h tpu3 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 0008 814ah tpu3 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 0008 814ch tpu3 timer general register c tgrc 16 16 2 or 3 pclkb 2 iclk 0008 814eh tpu3 timer general register d tgrd 16 16 2 or 3 pclkb 2 iclk 0008 8150h tpu4 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8151h tpu4 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 0008 8152h tpu4 timer i/o control register tior 8 8 2 or 3 pclkb 2 iclk 0008 8154h tpu4 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 0008 8155h tpu4 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 0008 8156h tpu4 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 0008 8158h tpu4 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 0008 815ah tpu4 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 0008 8160h tpu5 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8161h tpu5 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 0008 8162h tpu5 timer i/o control register tior 8 8 2 or 3 pclkb 2 iclk 0008 8164h tpu5 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 0008 8165h tpu5 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 0008 8166h tpu5 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 0008 8168h tpu5 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 0008 816ah tpu5 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (13 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 56 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 8200h tmr0 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8201h tmr1 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8202h tmr0 timer control/status register tcsr 8 8 2 or 3 pclkb 2 iclk 0008 8203h tmr1 timer control/status register tcsr 8 8 2 or 3 pclkb 2 iclk 0008 8204h tmr0 time constant register a tcora 8 8 2 or 3 pclkb 2 iclk 0008 8205h tmr1 time constant register a tcora 8 8* 1 2 or 3 pclkb 2 iclk 0008 8206h tmr0 time constant register b tcorb 8 8 2 or 3 pclkb 2 iclk 0008 8207h tmr1 time constant register b tcorb 8 8* 1 2 or 3 pclkb 2 iclk 0008 8208h tmr0 timer counter tcnt 8 8 2 or 3 pclkb 2 iclk 0008 8209h tmr1 timer counter tcnt 8 8* 1 2 or 3 pclkb 2 iclk 0008 820ah tmr0 timer counter control register tccr 8 8 2 or 3 pclkb 2 iclk 0008 820bh tmr1 timer counter control register tccr 8 8* 1 2 or 3 pclkb 2 iclk 0008 820ch tmr0 timer count start register tcstr 8 8 2 or 3 pclkb 2 iclk 0008 8210h tmr2 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8211h tmr3 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 8212h tmr2 timer control/status register tcsr 8 8 2 or 3 pclkb 2 iclk 0008 8213h tmr3 timer control/status register tcsr 8 8 2 or 3 pclkb 2 iclk 0008 8214h tmr2 time constant register a tcora 8 8 2 or 3 pclkb 2 iclk 0008 8215h tmr3 time constant register a tcora 8 8* 1 2 or 3 pclkb 2 iclk 0008 8216h tmr2 time constant register b tcorb 8 8 2 or 3 pclkb 2 iclk 0008 8217h tmr3 time constant register b tcorb 8 8* 1 2 or 3 pclkb 2 iclk 0008 8218h tmr2 timer counter tcnt 8 8 2 or 3 pclkb 2 iclk 0008 8219h tmr3 timer counter tcnt 8 8* 1 2 or 3 pclkb 2 iclk 0008 821ah tmr2 timer counter control register tccr 8 8 2 or 3 pclkb 2 iclk 0008 821bh tmr3 timer counter control register tccr 8 8* 1 2 or 3 pclkb 2 iclk 0008 821ch tmr2 timer count start register tcstr 8 8 2 or 3 pclkb 2 iclk 0008 8280h crc crc control register crccr 8 8 2 or 3 pclkb 2 iclk 0008 8281h crc crc data input register crcdir 8 8 2 or 3 pclkb 2 iclk 0008 8282h crc crc data output register crcdor 16 16 2 or 3 pclkb 2 iclk 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2 or 3 pclkb 2 iclk 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2 or 3 pclkb 2 iclk 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2 or 3 pclkb 2 iclk 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2 or 3 pclkb 2 iclk 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2 or 3 pclkb 2 iclk 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2 or 3 pclkb 2 iclk 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2 or 3 pclkb 2 iclk 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2 or 3 pclkb 2 iclk 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2 or 3 pclkb 2 iclk 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2 or 3 pclkb 2 iclk 0008 830ah riic0 slave address register l0 sarl0 8 8 2 or 3 pclkb 2 iclk 0008 830bh riic0 slave address register u0 saru0 8 8 2 or 3 pclkb 2 iclk 0008 830ch riic0 slave address register l1 sarl1 8 8 2 or 3 pclkb 2 iclk 0008 830dh riic0 slave address register u1 saru1 8 8 2 or 3 pclkb 2 iclk 0008 830eh riic0 slave address register l2 sarl2 8 8 2 or 3 pclkb 2 iclk 0008 830fh riic0 slave address register u2 saru2 8 8 2 or 3 pclkb 2 iclk 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2 or 3 pclkb 2 iclk 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2 or 3 pclkb 2 iclk 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2 or 3 pclkb 2 iclk 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2 or 3 pclkb 2 iclk 0008 8380h rspi0 rspi control register spcr 8 8 2 or 3 pclkb 2 iclk 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2 or 3 pclkb 2 iclk 0008 8382h rspi0 rspi pin control register sppcr 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (14 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 57 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 8383h rspi0 rspi status register spsr 8 8 2 or 3 pclkb 2 iclk 0008 8384h rspi0 rspi data register spdr 32 16, 32 2 or 3 pclkb 2 iclk 0008 8388h rspi0 rspi sequence control register spscr 8 8 2 or 3 pclkb 2 iclk 0008 8389h rspi0 rspi sequence status register spssr 8 8 2 or 3 pclkb 2 iclk 0008 838ah rspi0 rspi bit rate register spbr 8 8 2 or 3 pclkb 2 iclk 0008 838bh rspi0 rspi data control register spdcr 8 8 2 or 3 pclkb 2 iclk 0008 838ch rspi0 rspi clock delay register spckd 8 8 2 or 3 pclkb 2 iclk 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2 or 3 pclkb 2 iclk 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2 or 3 pclkb 2 iclk 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2 or 3 pclkb 2 iclk 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2 or 3 pclkb 2 iclk 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2 or 3 pclkb 2 iclk 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2 or 3 pclkb 2 iclk 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2 or 3 pclkb 2 iclk 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2 or 3 pclkb 2 iclk 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2 or 3 pclkb 2 iclk 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2 or 3 pclkb 2 iclk 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2 or 3 pclkb 2 iclk 0008 8410h irda irda control register ircr 8 8 2 or 3 pclkb 2 iclk 0008 8900h poe input level control/status register 1 icsr1 16 8, 16 2 or 3 pclkb 2 iclk 0008 8902h poe output level control/status register 1 ocsr1 16 8, 16 2 or 3 pclkb 2 iclk 0008 8908h poe input level control/status register 2 icsr2 16 8, 16 2 or 3 pclkb 2 iclk 0008 890ah poe software port output enable register spoer 8 8 2 or 3 pclkb 2 iclk 0008 890bh poe port output enable control register 1 poecr1 8 8 2 or 3 pclkb 2 iclk 0008 890ch poe port output enable control register 2 poecr2 8 8 2 or 3 pclkb 2 iclk 0008 890eh poe input level control/status register 3 icsr3 16 8, 16 2 or 3 pclkb 2 iclk 0008 9000h s12ad a/d control register adcsr 16 16 2 or 3 pclkb 2 iclk 0008 9004h s12ad a/d channel select register a0 adansa0 16 16 2 or 3 pclkb 2 iclk 0008 9006h s12ad a/d channel select register a1 adansa1 16 16 2 or 3 pclkb 2 iclk 0008 9008h s12ad a/d-converted value addition/average function select register 0 adads0 16 16 2 or 3 pclkb 2 iclk 0008 900ah s12ad a/d-converted value addition/average function select register 1 adads1 16 16 2 or 3 pclkb 2 iclk 0008 900ch s12ad a/d-converted value addition/average count select register adadc 8 8 2 or 3 pclkb 2 iclk 0008 900eh s12ad a/d control extended register adcer 16 16 2 or 3 pclkb 2 iclk 0008 9010h s12ad a/d conversion start trigger select register adstrgr 16 16 2 or 3 pclkb 2 iclk 0008 9012h s12ad a/d conversion extended input control register adexicr 16 16 2 or 3 pclkb 2 iclk 0008 9014h s12ad a/d channel select register b0 adansb0 16 16 2 or 3 pclkb 2 iclk 0008 9016h s12ad a/d channel select register b1 adansb1 16 16 2 or 3 pclkb 2 iclk 0008 9018h s12ad a/d data duplication register addbldr 16 16 2 or 3 pclkb 2 iclk 0008 901ah s12ad a/d temperature sensor data register adtsdr 16 16 2 or 3 pclkb 2 iclk 0008 901ch s12ad a/d internal reference voltage data register adocdr 16 16 2 or 3 pclkb 2 iclk 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2 or 3 pclkb 2 iclk 0008 9020h s12ad a/d data register 0 addr0 16 16 2 or 3 pclkb 2 iclk 0008 9022h s12ad a/d data register 1 addr1 16 16 2 or 3 pclkb 2 iclk 0008 9024h s12ad a/d data register 2 addr2 16 16 2 or 3 pclkb 2 iclk 0008 9026h s12ad a/d data register 3 addr3 16 16 2 or 3 pclkb 2 iclk 0008 9028h s12ad a/d data register 4 addr4 16 16 2 or 3 pclkb 2 iclk 0008 902ah s12ad a/d data register 5 addr5 16 16 2 or 3 pclkb 2 iclk 0008 902ch s12ad a/d data register 6 addr6 16 16 2 or 3 pclkb 2 iclk 0008 902eh s12ad a/d data register 7 addr7 16 16 2 or 3 pclkb 2 iclk 0008 9040h s12ad a/d data register 16 addr16 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (15 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 58 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 9042h s12ad a/d data register 17 addr17 16 16 2 or 3 pclkb 2 iclk 0008 9044h s12ad a/d data register 18 addr18 16 16 2 or 3 pclkb 2 iclk 0008 9046h s12ad a/d data register 19 addr19 16 16 2 or 3 pclkb 2 iclk 0008 9048h s12ad a/d data register 20 addr20 16 16 2 or 3 pclkb 2 iclk 0008 904ah s12ad a/d data register 21 addr21 16 16 2 or 3 pclkb 2 iclk 0008 904ch s12ad a/d data register 22 addr22 16 16 2 or 3 pclkb 2 iclk 0008 904eh s12ad a/d data register 23 addr23 16 16 2 or 3 pclkb 2 iclk 0008 9050h s12ad a/d data register 24 addr24 16 16 2 or 3 pclkb 2 iclk 0008 9052h s12ad a/d data register 25 addr25 16 16 2 or 3 pclkb 2 iclk 0008 9055h s12ad a/d data register 26 addr26 16 16 2 or 3 pclkb 2 iclk 0008 9056h s12ad a/d data register 27 addr27 16 16 2 or 3 pclkb 2 iclk 0008 9058h s12ad a/d data register 28 addr28 16 16 2 or 3 pclkb 2 iclk 0008 905ah s12ad a/d data register 29 addr29 16 16 2 or 3 pclkb 2 iclk 0008 905ch s12ad a/d data register 30 addr30 16 16 2 or 3 pclkb 2 iclk 0008 905eh s12ad a/d data register 31 addr31 16 16 2 or 3 pclkb 2 iclk 0008 907ah s12ad a/d disconnection detection control register addiscr 8 8 2 or 3 pclkb 2 iclk 0008 907dh s12ad a/d event link control register adelccr 8 8 2 or 3 pclkb 2 iclk 0008 9080h s12ad a/d group scan priority control register adgspcr 16 16 2 or 3 pclkb 2 iclk 0008 908ah s12ad a/d high-side/low-side reference voltage control register adhvrefcnt 8 8 2 or 3 pclkb 2 iclk 0008 908ch s12ad a/d compare function window a/b status monitor register adwinmon 8 8 2 or 3 pclkb 2 iclk 0008 9090h s12ad a/d compare function control register adcmpcr 16 16 2 or 3 pclkb 2 iclk 0008 9092h s12ad a/d compare function window a extended input select register adcmpanser 8 8 2 or 3 pclkb 2 iclk 0008 9093h s12ad a/d compare function window a extended input comparison condition setting register adcmpler 8 8 2 or 3 pclkb 2 iclk 0008 9094h s12ad a/d compare function window a channel select register 0 adcmpansr0 16 16 2 or 3 pclkb 2 iclk 0008 9096h s12ad a/d compare function window a channel select register 1 adcmpansr1 16 16 2 or 3 pclkb 2 iclk 0008 9098h s12ad a/d compare function window a comparison condition setting register 0 adcmplr0 16 16 2 or 3 pclkb 2 iclk 0008 909ah s12ad a/d compare function window a comparison condition setting register 1 adcmplr1 16 16 2 or 3 pclkb 2 iclk 0008 909ch s12ad a/d compare function window a lower-side level setting register adcmpdr0 16 16 2 or 3 pclkb 2 iclk 0008 909eh s12ad a/d compare function window a upper-side level setting register adcmpdr1 16 16 2 or 3 pclkb 2 iclk 0008 90a0h s12ad a/d compare function window a channel status register 0 adcmpsr0 16 16 2 or 3 pclkb 2 iclk 0008 90a2h s12ad a/d compare function window a channel status register 1 adcmpsr1 16 16 2 or 3 pclkb 2 iclk 0008 90a4h s12ad a/d compare function window a extended input channel status register adcmpser 16 16 2 or 3 pclkb 2 iclk 0008 90a6h s12ad a/d compare function window b channel select register adcmpbnsr 8 8 2 or 3 pclkb 2 iclk 0008 90a8h s12ad a/d compare function window b lower-side level setting register adwinllb 16 16 2 or 3 pclkb 2 iclk 0008 90aah s12ad a/d compare function window b upper-side level setting register adwinulb 16 16 2 or 3 pclkb 2 iclk 0008 90ach s12ad a/d compare function window b channel status register adcmpbsr 8 8 2 or 3 pclkb 2 iclk 0008 90b0h s12ad a/d data storage buffer register 0 adbuf0 16 16 2 or 3 pclkb 2 iclk 0008 90b2h s12ad a/d data storage buffer register 1 adbuf1 16 16 2 or 3 pclkb 2 iclk 0008 90b4h s12ad a/d data storage buffer register 2 adbuf2 16 16 2 or 3 pclkb 2 iclk 0008 90b6h s12ad a/d data storage buffer register 3 adbuf3 16 16 2 or 3 pclkb 2 iclk 0008 90b8h s12ad a/d data storage buffer register 4 adbuf4 16 16 2 or 3 pclkb 2 iclk 0008 90bah s12ad a/d data storage buffer register 5 adbuf5 16 16 2 or 3 pclkb 2 iclk 0008 90bch s12ad a/d data storage buffer register 6 adbuf6 16 16 2 or 3 pclkb 2 iclk 0008 90beh s12ad a/d data storage buffer register 7 adbuf7 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (16 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 59 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 90c0h s12ad a/d data storage buffer register 8 adbuf8 16 16 2 or 3 pclkb 2 iclk 0008 90c2h s12ad a/d data storage buffer register 9 adbuf9 16 16 2 or 3 pclkb 2 iclk 0008 90c4h s12ad a/d data storage buffer register 10 adbuf10 16 16 2 or 3 pclkb 2 iclk 0008 90c6h s12ad a/d data storage buffer register 11 adbuf11 16 16 2 or 3 pclkb 2 iclk 0008 90c8h s12ad a/d data storage buffer register 12 adbuf12 16 16 2 or 3 pclkb 2 iclk 0008 90cah s12ad a/d data storage buffer register 13 adbuf13 16 16 2 or 3 pclkb 2 iclk 0008 90cch s12ad a/d data storage buffer register 14 adbuf14 16 16 2 or 3 pclkb 2 iclk 0008 90ceh s12ad a/d data storage buffer register 15 adbuf15 16 16 2 or 3 pclkb 2 iclk 0008 90d0h s12ad a/d data storage buffer enable register adbufen 8 8 2 or 3 pclkb 2 iclk 0008 90d2h s12ad a/d data storage buffer pointer register adbufptr 8 8 2 or 3 pclkb 2 iclk 0008 90ddh s12ad a/d sampling state register l adsstrl 8 8 2 or 3 pclkb 2 iclk 0008 90deh s12ad a/d sampling state register t adsstrt 8 8 2 or 3 pclkb 2 iclk 0008 90dfh s12ad a/d sampling state register o adsstro 8 8 2 or 3 pclkb 2 iclk 0008 90e0h s12ad a/d sampling state register 0 adsstr0 8 8 2 or 3 pclkb 2 iclk 0008 90e1h s12ad a/d sampling state register 1 adsstr1 8 8 2 or 3 pclkb 2 iclk 0008 90e2h s12ad a/d sampling state register 2 adsstr2 8 8 2 or 3 pclkb 2 iclk 0008 90e3h s12ad a/d sampling state register 3 adsstr3 8 8 2 or 3 pclkb 2 iclk 0008 90e4h s12ad a/d sampling state register 4 adsstr4 8 8 2 or 3 pclkb 2 iclk 0008 90e5h s12ad a/d sampling state register 5 adsstr5 8 8 2 or 3 pclkb 2 iclk 0008 90e6h s12ad a/d sampling state register 6 adsstr6 8 8 2 or 3 pclkb 2 iclk 0008 90e7h s12ad a/d sampling state register 7 adsstr7 8 8 2 or 3 pclkb 2 iclk 0008 a000h sci0 serial mode register smr 8 8 2 or 3 pclkb 2 iclk 0008 a001h sci0 bit rate register brr 8 8 2 or 3 pclkb 2 iclk 0008 a002h sci0 serial control register scr 8 8 2 or 3 pclkb 2 iclk 0008 a003h sci0 transmit data register tdr 8 8 2 or 3 pclkb 2 iclk 0008 a004h sci0 serial status register ssr 8 8 2 or 3 pclkb 2 iclk 0008 a005h sci0 receive data register rdr 8 8 2 or 3 pclkb 2 iclk 0008 a006h sci0 smart card mode register scmr 8 8 2 or 3 pclkb 2 iclk 0008 a007h sci0 serial extended mode register semr 8 8 2 or 3 pclkb 2 iclk 0008 a008h sci0 noise filter setting register snfr 8 8 2 or 3 pclkb 2 iclk 0008 a009h sci0 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 2 iclk 0008 a00ah sci0 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 2 iclk 0008 a00bh sci0 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 2 iclk 0008 a00ch sci0 i 2 c status register sisr 8 8 2 or 3 pclkb 2 iclk 0008 a00dh sci0 spi mode register spmr 8 8 2 or 3 pclkb 2 iclk 0008 a00eh sci0 transmit data register hl tdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a00eh sci0 transmit data register h tdrh 8 8 2 or 3 pclkb 2 iclk 0008 a00fh sci0 transmit data register l tdrl 8 8 2 or 3 pclkb 2 iclk 0008 a010h sci0 receive data register hl rdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a010h sci0 receive data register h rdrh 8 8 2 or 3 pclkb 2 iclk 0008 a011h sci0 receive data register l rdrl 8 8 2 or 3 pclkb 2 iclk 0008 a012h sci0 modulation duty register mddr 8 8 2 or 3 pclkb 2 iclk 0008 a020h sci1 serial mode register smr 8 8 2 or 3 pclkb 2 iclk 0008 a021h sci1 bit rate register brr 8 8 2 or 3 pclkb 2 iclk 0008 a022h sci1 serial control register scr 8 8 2 or 3 pclkb 2 iclk 0008 a023h sci1 transmit data register tdr 8 8 2 or 3 pclkb 2 iclk 0008 a024h sci1 serial status register ssr 8 8 2 or 3 pclkb 2 iclk 0008 a025h sci1 receive data register rdr 8 8 2 or 3 pclkb 2 iclk 0008 a026h sci1 smart card mode register scmr 8 8 2 or 3 pclkb 2 iclk 0008 a027h sci1 serial extended mode register semr 8 8 2 or 3 pclkb 2 iclk 0008 a028h sci1 noise filter setting register snfr 8 8 2 or 3 pclkb 2 iclk 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (17 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 60 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 2 iclk 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 2 iclk 0008 a02ch sci1 i 2 c status register sisr 8 8 2 or 3 pclkb 2 iclk 0008 a02dh sci1 spi mode register spmr 8 8 2 or 3 pclkb 2 iclk 0008 a02eh sci1 transmit data register hl tdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a02eh sci1 transmit data register h tdrh 8 8 2 or 3 pclkb 2 iclk 0008 a02fh sci1 transmit data register l tdrl 8 8 2 or 3 pclkb 2 iclk 0008 a030h sci1 receive data register hl rdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a030h sci1 receive data register h rdrh 8 8 2 or 3 pclkb 2 iclk 0008 a031h sci1 receive data register l rdrl 8 8 2 or 3 pclkb 2 iclk 0008 a032h sci1 modulation duty register mddr 8 8 2 or 3 pclkb 2 iclk 0008 a0a0h sci5 serial mode register smr 8 8 2 or 3 pclkb 2 iclk 0008 a0a1h sci5 bit rate register brr 8 8 2 or 3 pclkb 2 iclk 0008 a0a2h sci5 serial control register scr 8 8 2 or 3 pclkb 2 iclk 0008 a0a3h sci5 transmit data register tdr 8 8 2 or 3 pclkb 2 iclk 0008 a0a4h sci5 serial status register ssr 8 8 2 or 3 pclkb 2 iclk 0008 a0a5h sci5 receive data register rdr 8 8 2 or 3 pclkb 2 iclk 0008 a0a6h sci5 smart card mode register scmr 8 8 2 or 3 pclkb 2 iclk 0008 a0a7h sci5 serial extended mode register semr 8 8 2 or 3 pclkb 2 iclk 0008 a0a8h sci5 noise filter setting register snfr 8 8 2 or 3 pclkb 2 iclk 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 2 iclk 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 2 iclk 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 2 iclk 0008 a0ach sci5 i 2 c status register sisr 8 8 2 or 3 pclkb 2 iclk 0008 a0adh sci5 spi mode register spmr 8 8 2 or 3 pclkb 2 iclk 0008 a0aeh sci5 transmit data register hl tdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a0aeh sci5 transmit data register h tdrh 8 8 2 or 3 pclkb 2 iclk 0008 a0afh sci5 transmit data register l tdrl 8 8 2 or 3 pclkb 2 iclk 0008 a0b0h sci5 receive data register hl rdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a0b0h sci5 receive data register h rdrh 8 8 2 or 3 pclkb 2 iclk 0008 a0b1h sci5 receive data register l rdrl 8 8 2 or 3 pclkb 2 iclk 0008 a0b2h sci5 modulation duty register mddr 8 8 2 or 3 pclkb 2 iclk 0008 a0c0h sci6 serial mode register smr 8 8 2 or 3 pclkb 2 iclk 0008 a0c1h sci6 bit rate register brr 8 8 2 or 3 pclkb 2 iclk 0008 a0c2h sci6 serial control register scr 8 8 2 or 3 pclkb 2 iclk 0008 a0c3h sci6 transmit data register tdr 8 8 2 or 3 pclkb 2 iclk 0008 a0c4h sci6 serial status register ssr 8 8 2 or 3 pclkb 2 iclk 0008 a0c5h sci6 receive data register rdr 8 8 2 or 3 pclkb 2 iclk 0008 a0c6h sci6 smart card mode register scmr 8 8 2 or 3 pclkb 2 iclk 0008 a0c7h sci6 serial extended mode register semr 8 8 2 or 3 pclkb 2 iclk 0008 a0c8h sci6 noise filter setting register snfr 8 8 2 or 3 pclkb 2 iclk 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 2 iclk 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 2 iclk 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 2 iclk 0008 a0cch sci6 i 2 c status register sisr 8 8 2 or 3 pclkb 2 iclk 0008 a0cdh sci6 spi mode register spmr 8 8 2 or 3 pclkb 2 iclk 0008 a0ceh sci6 transmit data register hl tdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a0ceh sci6 transmit data register h tdrh 8 8 2 or 3 pclkb 2 iclk 0008 a0cfh sci6 transmit data register l tdrl 8 8 2 or 3 pclkb 2 iclk 0008 a0d0h sci6 receive data register hl rdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a0d0h sci6 receive data register h rdrh 8 8 2 or 3 pclkb 2 iclk 0008 a0d1h sci6 receive data register l rdrl 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (18 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 61 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 a0d2h sci6 modulation duty register mddr 8 8 2 or 3 pclkb 2 iclk 0008 a100h sci8 serial mode register smr 8 8 2 or 3 pclkb 2 iclk 0008 a101h sci8 bit rate register brr 8 8 2 or 3 pclkb 2 iclk 0008 a102h sci8 serial control register scr 8 8 2 or 3 pclkb 2 iclk 0008 a103h sci8 transmit data register tdr 8 8 2 or 3 pclkb 2 iclk 0008 a104h sci8 serial status register ssr 8 8 2 or 3 pclkb 2 iclk 0008 a105h sci8 receive data register rdr 8 8 2 or 3 pclkb 2 iclk 0008 a106h sci8 smart card mode register scmr 8 8 2 or 3 pclkb 2 iclk 0008 a107h sci8 serial extended mode register semr 8 8 2 or 3 pclkb 2 iclk 0008 a108h sci8 noise filter setting register snfr 8 8 2 or 3 pclkb 2 iclk 0008 a109h sci8 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 2 iclk 0008 a10ah sci8 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 2 iclk 0008 a10bh sci8 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 2 iclk 0008 a10ch sci8 i 2 c status register sisr 8 8 2 or 3 pclkb 2 iclk 0008 a10dh sci8 spi mode register spmr 8 8 2 or 3 pclkb 2 iclk 0008 a10eh sci8 transmit data register hl tdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a10eh sci8 transmit data register h tdrh 8 8 2 or 3 pclkb 2 iclk 0008 a10fh sci8 transmit data register l tdrl 8 8 2 or 3 pclkb 2 iclk 0008 a110h sci8 receive data register hl rdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a110h sci8 receive data register h rdrh 8 8 2 or 3 pclkb 2 iclk 0008 a111h sci8 receive data register l rdrl 8 8 2 or 3 pclkb 2 iclk 0008 a112h sci8 modulation duty register mddr 8 8 2 or 3 pclkb 2 iclk 0008 a120h sci9 serial mode register smr 8 8 2 or 3 pclkb 2 iclk 0008 a121h sci9 bit rate register brr 8 8 2 or 3 pclkb 2 iclk 0008 a122h sci9 serial control register scr 8 8 2 or 3 pclkb 2 iclk 0008 a123h sci9 transmit data register tdr 8 8 2 or 3 pclkb 2 iclk 0008 a124h sci9 serial status register ssr 8 8 2 or 3 pclkb 2 iclk 0008 a125h sci9 receive data register rdr 8 8 2 or 3 pclkb 2 iclk 0008 a126h sci9 smart card mode register scmr 8 8 2 or 3 pclkb 2 iclk 0008 a127h sci9 serial extended mode register semr 8 8 2 or 3 pclkb 2 iclk 0008 a128h sci9 noise filter setting register snfr 8 8 2 or 3 pclkb 2 iclk 0008 a129h sci9 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 2 iclk 0008 a12ah sci9 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 2 iclk 0008 a12bh sci9 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 2 iclk 0008 a12ch sci9 i 2 c status register sisr 8 8 2 or 3 pclkb 2 iclk 0008 a12dh sci9 spi mode register spmr 8 8 2 or 3 pclkb 2 iclk 0008 a12eh sci9 transmit data register hl tdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a12eh sci9 transmit data register h tdrh 8 8 2 or 3 pclkb 2 iclk 0008 a12fh sci9 transmit data register l tdrl 8 8 2 or 3 pclkb 2 iclk 0008 a130h sci9 receive data register hl rdrhl 16 16 4 or 5 pclkb 2 iclk 0008 a130h sci9 receive data register h rdrh 8 8 2 or 3 pclkb 2 iclk 0008 a131h sci9 receive data register l rdrl 8 8 2 or 3 pclkb 2 iclk 0008 a132h sci9 modulation duty register mddr 8 8 2 or 3 pclkb 2 iclk 0008 a500h ssi0 control register ssicr 32 32 2 or 3 pclkb 2 iclk 0008 a504h ssi0 status register ssisr 32 32 2 or 3 pclkb 2 iclk 0008 a510h ssi0 fifo control register ssifcr 32 32 2 or 3 pclkb 2 iclk 0008 a514h ssi0 fifo status register ssifsr 32 32 2 or 3 pclkb 2 iclk 0008 a518h ssi0 transmit fifo data register ssiftdr 32 32 2 or 3 pclkb 2 iclk 0008 a51ch ssi0 receive fifo data register ssifrdr 32 32 2 or 3 pclkb 2 iclk 0008 a520h ssi0 tdm mode register ssitdmr 32 32 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (19 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 62 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 ac00h sdhi command register sdcmd 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac08h sdhi argument register sdarg 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac10h sdhi data stop register sdstop 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac14h sdhi block count register sdblkcnt 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac18h sdhi response register 10 sdrsp10 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac20h sdhi response register 32 sdrsp32 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac28h sdhi response register 54 sdrsp54 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac30h sdhi response register 76 sdrsp76 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac38h sdhi sd status register 1 sdsts1 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac3ch sdhi sd status register 2 sdsts2 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac40h sdhi sd interrupt mask register 1 sdimsk1 32 32 3 or 4 pclkb cycles when re ading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac44h sdhi sd interrupt mask register 2 sdimsk2 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac48h sdhi sdhi clock control register sdclkcr 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing table 4.1 list of i/o register s (address order) (20 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 63 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 ac4ch sdhi transfer data size register sdsize 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac50h sdhi card access option register sdopt 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac58h sdhi sd error status register 1 sdersts1 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac5ch sdhi sd error status register 2 sdersts2 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac60h sdhi sd buffer register sdbufr 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac68h sdhi sdio mode control register sdiomd 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac6ch sdhi sdio status register sdiosts 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ac70h sdhi sdio interrupt mask register sdioimsk 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 adb0h sdhi dma transfer enable register sddmaen 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 adc0h sdhi sdhi software reset register sdrst 32 32 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 ade0h sdhi swap control register sdswap 32 32 3 or 4 pclkb cycles when re ading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 b000h cac cac control register 0 cacr0 8 8 2 or 3 pclkb 2 iclk 0008 b001h cac cac control register 1 cacr1 8 8 2 or 3 pclkb 2 iclk 0008 b002h cac cac control register 2 cacr2 8 8 2 or 3 pclkb 2 iclk 0008 b003h cac cac interrupt request enable register caicr 8 8 2 or 3 pclkb 2 iclk 0008 b004h cac cac status register castr 8 8 2 or 3 pclkb 2 iclk 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2 or 3 pclkb 2 iclk 0008 b008h cac cac lower-limit value setting register callvr 16 16 2 or 3 pclkb 2 iclk 0008 b00ah cac cac counter buffer register cacntbr 16 16 2 or 3 pclkb 2 iclk 0008 b080h doc doc control register docr 8 8 2 or 3 pclkb 2 iclk 0008 b082h doc doc data input register dodir 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (21 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 64 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 b084h doc doc data setting register dodsr 16 16 2 or 3 pclkb 2 iclk 0008 b100h elc event link control register elcr 8 8 2 or 3 pclkb 2 iclk 0008 b102h elc event link setting register 1 elsr1 8 8 2 or 3 pclkb 2 iclk 0008 b103h elc event link setting register 2 elsr2 8 8 2 or 3 pclkb 2 iclk 0008 b104h elc event link setting register 3 elsr3 8 8 2 or 3 pclkb 2 iclk 0008 b105h elc event link setting register 4 elsr4 8 8 2 or 3 pclkb 2 iclk 0008 b108h elc event link setting register 7 elsr7 8 8 2 or 3 pclkb 2 iclk 0008 b109h elc event link setting register 8 elsr8 8 8 2 or 3 pclkb 2 iclk 0008 b10bh elc event link setting register 10 elsr10 8 8 2 or 3 pclkb 2 iclk 0008 b10dh elc event link setting register 12 elsr12 8 8 2 or 3 pclkb 2 iclk 0008 b10fh elc event link setting register 14 elsr14 8 8 2 or 3 pclkb 2 iclk 0008 b110h elc event link setting register 15 elsr15 8 8 2 or 3 pclkb 2 iclk 0008 b111h elc event link setting register 16 elsr16 8 8 2 or 3 pclkb 2 iclk 0008 b113h elc event link setting register 18 elsr18 8 8 2 or 3 pclkb 2 iclk 0008 b114h elc event link setting register 19 elsr19 8 8 2 or 3 pclkb 2 iclk 0008 b115h elc event link setting register 20 elsr20 8 8 2 or 3 pclkb 2 iclk 0008 b116h elc event link setting register 21 elsr21 8 8 2 or 3 pclkb 2 iclk 0008 b117h elc event link setting register 22 elsr22 8 8 2 or 3 pclkb 2 iclk 0008 b118h elc event link setting register 23 elsr23 8 8 2 or 3 pclkb 2 iclk 0008 b119h elc event link setting register 24 elsr24 8 8 2 or 3 pclkb 2 iclk 0008 b11ah elc event link setting register 25 elsr25 8 8 2 or 3 pclkb 2 iclk 0008 b11bh elc event link setting register 26 elsr26 8 8 2 or 3 pclkb 2 iclk 0008 b11ch elc event link setting register 27 elsr27 8 8 2 or 3 pclkb 2 iclk 0008 b11dh elc event link setting register 28 elsr28 8 8 2 or 3 pclkb 2 iclk 0008 b11eh elc event link setting register 29 elsr29 8 8 2 or 3 pclkb 2 iclk 0008 b11fh elc event link option setting register a elopa 8 8 2 or 3 pclkb 2 iclk 0008 b120h elc event link option setting register b elopb 8 8 2 or 3 pclkb 2 iclk 0008 b121h elc event link option setting register c elopc 8 8 2 or 3 pclkb 2 iclk 0008 b122h elc event link option setting register d elopd 8 8 2 or 3 pclkb 2 iclk 0008 b123h elc port group setting register 1 pgr1 8 8 2 or 3 pclkb 2 iclk 0008 b124h elc port group setting register 2 pgr2 8 8 2 or 3 pclkb 2 iclk 0008 b125h elc port group control register 1 pgc1 8 8 2 or 3 pclkb 2 iclk 0008 b126h elc port group control register 2 pgc2 8 8 2 or 3 pclkb 2 iclk 0008 b127h elc port buffer register 1 pdbf1 8 8 2 or 3 pclkb 2 iclk 0008 b128h elc port buffer register 2 pdbf2 8 8 2 or 3 pclkb 2 iclk 0008 b129h elc event link port setting register 0 pel0 8 8 2 or 3 pclkb 2 iclk 0008 b12ah elc event link port setting register 1 pel1 8 8 2 or 3 pclkb 2 iclk 0008 b12bh elc event link port setting register 2 pel2 8 8 2 or 3 pclkb 2 iclk 0008 b12ch elc event link port setting register 3 pel3 8 8 2 or 3 pclkb 2 iclk 0008 b12dh elc event link software event generation register elsegr 8 8 2 or 3 pclkb 2 iclk 0008 b300h sci12 serial mode register smr 8 8 2 or 3 pclkb 2 iclk 0008 b301h sci12 bit rate register brr 8 8 2 or 3 pclkb 2 iclk 0008 b302h sci12 serial control register scr 8 8 2 or 3 pclkb 2 iclk 0008 b303h sci12 transmit data register tdr 8 8 2 or 3 pclkb 2 iclk 0008 b304h sci12 serial status register ssr 8 8 2 or 3 pclkb 2 iclk 0008 b305h sci12 receive data register rdr 8 8 2 or 3 pclkb 2 iclk 0008 b306h sci12 smart card mode register scmr 8 8 2 or 3 pclkb 2 iclk 0008 b307h sci12 serial extended mode register semr 8 8 2 or 3 pclkb 2 iclk 0008 b308h sci12 noise filter setting register snfr 8 8 2 or 3 pclkb 2 iclk 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 2 iclk 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 2 iclk 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (22 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 65 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 b30ch sci12 i 2 c status register sisr 8 8 2 or 3 pclkb 2 iclk 0008 b30dh sci12 spi mode register spmr 8 8 2 or 3 pclkb 2 iclk 0008 b30eh sci12 transmit data register hl tdrhl 16 16 4 or 5 pclkb 2 iclk 0008 b30eh sci12 transmit data register h tdrh 8 8 2 or 3 pclkb 2 iclk 0008 b30fh sci12 transmit data register l tdrl 8 8 2 or 3 pclkb 2 iclk 0008 b310h sci12 receive data register hl rdrhl 16 16 4 or 5 pclkb 2 iclk 0008 b310h sci12 receive data register h rdrh 8 8 2 or 3 pclkb 2 iclk 0008 b311h sci12 receive data register l rdrl 8 8 2 or 3 pclkb 2 iclk 0008 b312h sci12 modulation duty register mddr 8 8 2 or 3 pclkb 2 iclk 0008 b320h sci12 extended serial module enable register esmer 8 8 2 or 3 pclkb 2 iclk 0008 b321h sci12 control register 0 cr0 8 8 2 or 3 pclkb 2 iclk 0008 b322h sci12 control register 1 cr1 8 8 2 or 3 pclkb 2 iclk 0008 b323h sci12 control register 2 cr2 8 8 2 or 3 pclkb 2 iclk 0008 b324h sci12 control register 3 cr3 8 8 2 or 3 pclkb 2 iclk 0008 b325h sci12 port control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 b326h sci12 interrupt control register icr 8 8 2 or 3 pclkb 2 iclk 0008 b327h sci12 status register str 8 8 2 or 3 pclkb 2 iclk 0008 b328h sci12 status clear register stcr 8 8 2 or 3 pclkb 2 iclk 0008 b329h sci12 control field 0 data register cf0dr 8 8 2 or 3 pclkb 2 iclk 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2 or 3 pclkb 2 iclk 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2 or 3 pclkb 2 iclk 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2 or 3 pclkb 2 iclk 0008 b32dh sci12 secondary control field 1 data register scf1dr 8 8 2 or 3 pclkb 2 iclk 0008 b32eh sci12 control field 1 compare enable register cf1cr 8 8 2 or 3 pclkb 2 iclk 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2 or 3 pclkb 2 iclk 0008 b330h sci12 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 0008 b331h sci12 timer mode register tmr 8 8 2 or 3 pclkb 2 iclk 0008 b332h sci12 timer prescaler register tpre 8 8 2 or 3 pclkb 2 iclk 0008 b333h sci12 timer count register tcnt 8 8 2 or 3 pclkb 2 iclk 0008 c000h port0 port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c001h port1 port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c002h port2 port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c003h port3 port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c004h port4 port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c005h port5 port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c00ah porta port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c00bh portb port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c00ch portc port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c00dh portd port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c00eh porte port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c011h porth port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c012h portj port direction register pdr 8 8 2 or 3 pclkb 2 iclk 0008 c020h port0 port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c021h port1 port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c022h port2 port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c023h port3 port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c024h port4 port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c025h port5 port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c02ah porta port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c02bh portb port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c02ch portc port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c02dh portd port output data register podr 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (23 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 66 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 c02eh porte port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c031h porth port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c032h portj port output data register podr 8 8 2 or 3 pclkb 2 iclk 0008 c040h port0 port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c041h port1 port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c042h port2 port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c043h port3 port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c044h port4 port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c045h port5 port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04ah porta port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04bh portb port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04ch portc port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04dh portd port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04eh porte port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c051h porth port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c052h portj port input data r egister pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c060h port0 port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c061h port1 port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c062h port2 port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c063h port3 port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c064h port4 port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c065h port5 port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c06ah porta port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c06bh portb port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c06ch portc port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c06dh portd port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c06eh porte port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c071h porth port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c072h portj port mode register pmr 8 8 2 or 3 pclkb 2 iclk 0008 c082h port1 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (24 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 67 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 c083h port1 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c084h port2 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c087h port3 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c08ah port5 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c08bh port5 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c094h porta open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c095h porta open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c096h portb open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c097h portb open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c098h portc open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c099h portc open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c09ch porte open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c09dh porte open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c0a4h portj open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c0c0h port0 pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0c1h port1 pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0c2h port2 pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0c3h port3 pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0c4h port4 pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0c5h port5 pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0cah porta pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0cbh portb pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0cch portc pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0cdh portd pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0ceh porte pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0d1h porth pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0d2h portj pull-up control register pcr 8 8 2 or 3 pclkb 2 iclk 0008 c0e1h port1 drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0e2h port2 drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0e3h port3 drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0e5h port5 drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0eah porta drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0ebh portb drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0ech portc drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0edh portd drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0eeh porte drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0f1h porth drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c0f2h portj drive capacity control register dscr 8 8 2 or 3 pclkb 2 iclk 0008 c100h mpc cs output enable register pfcse 8 8 2 or 3 pclkb 2 iclk 0008 c104h mpc address output enable register 0 pfaoe0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c105h mpc address output enable register 1 pfaoe1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c106h mpc external bus control register 0 pfbcr0 8 8, 16 2 or 3 pclkb 2 iclk 0008 c107h mpc external bus control register 1 pfbcr1 8 8, 16 2 or 3 pclkb 2 iclk 0008 c11fh mpc write-protect register pwpr 8 8 2 or 3 pclkb 2 iclk 0008 c120h port port switching register b psrb 8 8 2 or 3 pclkb 2 iclk 0008 c121h port port switching register a psra 8 8 2 or 3 pclkb 2 iclk 0008 c143h mpc p03 pin function control register p03pfs 8 8 2 or 3 pclkb 2 iclk 0008 c145h mpc p05 pin function control register p05pfs 8 8 2 or 3 pclkb 2 iclk 0008 c147h mpc p07 pin function control register p07pfs 8 8 2 or 3 pclkb 2 iclk 0008 c14ah mpc p12 pin function control register p12pfs 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (25 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 68 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 c14bh mpc p13 pin function control register p13pfs 8 8 2 or 3 pclkb 2 iclk 0008 c14ch mpc p14 pin function control register p14pfs 8 8 2 or 3 pclkb 2 iclk 0008 c14dh mpc p15 pin function control register p15pfs 8 8 2 or 3 pclkb 2 iclk 0008 c14eh mpc p16 pin function control register p16pfs 8 8 2 or 3 pclkb 2 iclk 0008 c14fh mpc p17 pin function control register p17pfs 8 8 2 or 3 pclkb 2 iclk 0008 c150h mpc p20 pin function control register p20pfs 8 8 2 or 3 pclkb 2 iclk 0008 c151h mpc p21 pin function control register p21pfs 8 8 2 or 3 pclkb 2 iclk 0008 c152h mpc p22 pin function control register p22pfs 8 8 2 or 3 pclkb 2 iclk 0008 c153h mpc p23 pin function control register p23pfs 8 8 2 or 3 pclkb 2 iclk 0008 c154h mpc p24 pin function control register p24pfs 8 8 2 or 3 pclkb 2 iclk 0008 c155h mpc p25 pin function control register p25pfs 8 8 2 or 3 pclkb 2 iclk 0008 c156h mpc p26 pin function control register p26pfs 8 8 2 or 3 pclkb 2 iclk 0008 c157h mpc p27 pin function control register p27pfs 8 8 2 or 3 pclkb 2 iclk 0008 c158h mpc p30 pin function control register p30pfs 8 8 2 or 3 pclkb 2 iclk 0008 c159h mpc p31 pin function control register p31pfs 8 8 2 or 3 pclkb 2 iclk 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2 or 3 pclkb 2 iclk 0008 c15bh mpc p33 pin function control register p33pfs 8 8 2 or 3 pclkb 2 iclk 0008 c15ch mpc p34 pin function control register p34pfs 8 8 2 or 3 pclkb 2 iclk 0008 c160h mpc p40 pin function control register p40pfs 8 8 2 or 3 pclkb 2 iclk 0008 c161h mpc p41 pin function control register p41pfs 8 8 2 or 3 pclkb 2 iclk 0008 c162h mpc p42 pin function control register p42pfs 8 8 2 or 3 pclkb 2 iclk 0008 c163h mpc p43 pin function control register p43pfs 8 8 2 or 3 pclkb 2 iclk 0008 c164h mpc p44 pin function control register p44pfs 8 8 2 or 3 pclkb 2 iclk 0008 c165h mpc p45 pin function control register p45pfs 8 8 2 or 3 pclkb 2 iclk 0008 c166h mpc p46 pin function control register p46pfs 8 8 2 or 3 pclkb 2 iclk 0008 c167h mpc p47 pin function control register p47pfs 8 8 2 or 3 pclkb 2 iclk 0008 c168h mpc p50 pin function control register p50pfs 8 8 2 or 3 pclkb 2 iclk 0008 c169h mpc p51 pin function control register p51pfs 8 8 2 or 3 pclkb 2 iclk 0008 c16ah mpc p52 pin function control register p52pfs 8 8 2 or 3 pclkb 2 iclk 0008 c16bh mpc p53 pin function control register p53pfs 8 8 2 or 3 pclkb 2 iclk 0008 c16ch mpc p54 pin function control register p54pfs 8 8 2 or 3 pclkb 2 iclk 0008 c16dh mpc p55 pin function control register p55pfs 8 8 2 or 3 pclkb 2 iclk 0008 c190h mpc pa0 pin function control register pa0pfs 8 8 2 or 3 pclkb 2 iclk 0008 c191h mpc pa1 pin function control register pa1pfs 8 8 2 or 3 pclkb 2 iclk 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2 or 3 pclkb 2 iclk 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2 or 3 pclkb 2 iclk 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2 or 3 pclkb 2 iclk 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2 or 3 pclkb 2 iclk 0008 c196h mpc pa6 pin function control register pa6pfs 8 8 2 or 3 pclkb 2 iclk 0008 c197h mpc pa7 pin function control register pa7pfs 8 8 2 or 3 pclkb 2 iclk 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2 or 3 pclkb 2 iclk 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2 or 3 pclkb 2 iclk 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2 or 3 pclkb 2 iclk 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2 or 3 pclkb 2 iclk 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2 or 3 pclkb 2 iclk 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2 or 3 pclkb 2 iclk 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2 or 3 pclkb 2 iclk 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a0h mpc pc0 pin function control register pc0pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a1h mpc pc1 pin function control register pc1pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a2h mpc pc2 pin function control register pc2pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a3h mpc pc3 pin function control register pc3pfs 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (26 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 69 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 c1a4h mpc pc4 pin function control register pc4pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a5h mpc pc5 pin function control register pc5pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a6h mpc pc6 pin function control register pc6pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a7h mpc pc7 pin function control register pc7pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a8h mpc pd0 pin function control register pd0pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1a9h mpc pd1 pin function control register pd1pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1aah mpc pd2 pin function control register pd2pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1abh mpc pd3 pin function control register pd3pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1ach mpc pd4 pin function control register pd4pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1adh mpc pd5 pin function control register pd5pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1aeh mpc pd6 pin function control register pd6pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1afh mpc pd7 pin function control register pd7pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1b0h mpc pe0 pin function control register pe0pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1b1h mpc pe1 pin function control register pe1pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1b3h mpc pe3 pin function control register pe3pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1b4h mpc pe4 pin function control register pe4pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1b5h mpc pe5 pin function control register pe5pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1b6h mpc pe6 pin function control register pe6pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1b7h mpc pe7 pin function control register pe7pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1c8h mpc ph0 pin function control register ph0pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1c9h mpc ph1 pin function control register ph1pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1cah mpc ph2 pin function control register ph2pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1cbh mpc ph3 pin function control register ph3pfs 8 8 2 or 3 pclkb 2 iclk 0008 c1d3h mpc pj3 pin function control register pj3pfs 8 8 2 or 3 pclkb 2 iclk 0008 c290h system reset status register 0 rstsr0 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c291h system reset status register 1 rstsr1 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c297h system voltage monitoring circuit control register lvcmpcr 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c298h system voltage detection level select register lvdlvlr 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c29ah system voltage monitoring 1 circuit control register 0 lvd1cr0 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c29bh system voltage monitoring 2 circuit control register 0 lvd2cr0 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c29dh system vbatt control register vbattcr 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c29eh system vbatt status register vbattsr 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c29fh system vbatt pin voltage drop detection interrupt control register vbtlvdicr 8 8 4 or 5 pclkb 2 or 3 iclk 0008 c400h rtc 64-hz counter r64cnt 8 8 2 or 3 pclkb 2 iclk 0008 c402h rtc second counter rseccnt 8 8 2 or 3 pclkb 2 iclk 0008 c402h rtc binary counter 0 bcnt0 8 8 2 or 3 pclkb 2 iclk 0008 c404h rtc minute counter rmincnt 8 8 2 or 3 pclkb 2 iclk 0008 c404h rtc binary counter 1 bcnt1 8 8 2 or 3 pclkb 2 iclk 0008 c406h rtc hour counter rhrcnt 8 8 2 or 3 pclkb 2 iclk 0008 c406h rtc binary counter 2 bcnt2 8 8 2 or 3 pclkb 2 iclk 0008 c408h rtc day-of-week counter rwkcnt 8 8 2 or 3 pclkb 2 iclk 0008 c408h rtc binary counter 3 bcnt3 8 8 2 or 3 pclkb 2 iclk 0008 c40ah rtc date counter rdaycnt 8 8 2 or 3 pclkb 2 iclk 0008 c40ch rtc month counter rmoncnt 8 8 2 or 3 pclkb 2 iclk 0008 c40eh rtc year counter ryrcnt 16 16 2 or 3 pclkb 2 iclk 0008 c410h rtc second alarm register rsecar 8 8 2 or 3 pclkb 2 iclk 0008 c410h rtc binary counter 0 alarm register bcnt0ar 8 8 2 or 3 pclkb 2 iclk 0008 c412h rtc minute alarm register rminar 8 8 2 or 3 pclkb 2 iclk 0008 c412h rtc binary counter 1 alarm register bcnt1ar 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (27 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 70 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 c414h rtc hour alarm register rhrar 8 8 2 or 3 pclkb 2 iclk 0008 c414h rtc binary counter 2 alarm register bcnt2ar 8 8 2 or 3 pclkb 2 iclk 0008 c416h rtc day-of-week alarm register rwkar 8 8 2 or 3 pclkb 2 iclk 0008 c416h rtc binary counter 3 alarm register bcnt3ar 8 8 2 or 3 pclkb 2 iclk 0008 c418h rtc date alarm register rdayar 8 8 2 or 3 pclkb 2 iclk 0008 c418h rtc binary counter 0 alarm enable register bcnt0aer 8 8 2 or 3 pclkb 2 iclk 0008 c41ah rtc month alarm register rmonar 8 8 2 or 3 pclkb 2 iclk 0008 c41ah rtc binary counter 1 alarm enable register bcnt1aer 8 8 2 or 3 pclkb 2 iclk 0008 c41ch rtc year alarm register ryrar 16 16 2 or 3 pclkb 2 iclk 0008 c41ch rtc binary counter 2 alarm enable register bcnt2aer 16 16 2 or 3 pclkb 2 iclk 0008 c41eh rtc year alarm enable register ryraren 8 8 2 or 3 pclkb 2 iclk 0008 c41eh rtc binary counter 3 alarm enable register bcnt3aer 8 8 2 or 3 pclkb 2 iclk 0008 c422h rtc rtc control register 1 rcr1 8 8 2 or 3 pclkb 2 iclk 0008 c424h rtc rtc control register 2 rcr2 8 8 2 or 3 pclkb 2 iclk 0008 c426h rtc rtc control register 3 rcr3 8 8 2 or 3 pclkb 2 iclk 0008 c42eh rtc time error adjustment register radj 8 8 2 or 3 pclkb 2 iclk 0008 c440h rtc time capture control register 0 rtccr0 8 8 2 or 3 pclkb 2 iclk 0008 c442h rtc time capture control register 1 rtccr1 8 8 2 or 3 pclkb 2 iclk 0008 c444h rtc time capture control register 2 rtccr2 8 8 2 or 3 pclkb 2 iclk 0008 c452h rtc second capture register 0 rseccp0 8 8 2 or 3 pclkb 2 iclk 0008 c452h rtc bcnt0 capture register 0 bcnt0cp0 8 8 2 or 3 pclkb 2 iclk 0008 c454h rtc minute capture register 0 rmincp0 8 8 2 or 3 pclkb 2 iclk 0008 c454h rtc bcnt1 capture register 0 bcnt1cp0 8 8 2 or 3 pclkb 2 iclk 0008 c456h rtc hour capture register 0 rhrcp0 8 8 2 or 3 pclkb 2 iclk 0008 c456h rtc bcnt2 capture register 0 bcnt2cp0 8 8 2 or 3 pclkb 2 iclk 0008 c45ah rtc date capture register 0 rdaycp0 8 8 2 or 3 pclkb 2 iclk 0008 c45ah rtc bcnt3 capture register 0 bcnt3cp0 8 8 2 or 3 pclkb 2 iclk 0008 c45ch rtc month capture register 0 rmoncp0 8 8 2 or 3 pclkb 2 iclk 0008 c462h rtc second capture register 1 rseccp1 8 8 2 or 3 pclkb 2 iclk 0008 c462h rtc bcnt0 capture register 1 bcnt0cp1 8 8 2 or 3 pclkb 2 iclk 0008 c464h rtc minute capture register 1 rmincp1 8 8 2 or 3 pclkb 2 iclk 0008 c464h rtc bcnt1 capture register 1 bcnt1cp1 8 8 2 or 3 pclkb 2 iclk 0008 c466h rtc hour capture register 1 rhrcp1 8 8 2 or 3 pclkb 2 iclk 0008 c466h rtc bcnt2 capture register 1 bcnt2cp1 8 8 2 or 3 pclkb 2 iclk 0008 c46ah rtc date capture register 1 rdaycp1 8 8 2 or 3 pclkb 2 iclk 0008 c46ah rtc bcnt3 capture register 1 bcnt3cp1 8 8 2 or 3 pclkb 2 iclk 0008 c46ch rtc month capture register 1 rmoncp1 8 8 2 or 3 pclkb 2 iclk 0008 c472h rtc second capture register 2 rseccp2 8 8 2 or 3 pclkb 2 iclk 0008 c472h rtc bcnt0 capture register 2 bcnt0cp2 8 8 2 or 3 pclkb 2 iclk 0008 c474h rtc minute capture register 2 rmincp2 8 8 2 or 3 pclkb 2 iclk 0008 c474h rtc bcnt1 capture register 2 bcnt1cp2 8 8 2 or 3 pclkb 2 iclk 0008 c476h rtc hour capture register 2 rhrcp2 8 8 2 or 3 pclkb 2 iclk 0008 c476h rtc bcnt2 capture register 2 bcnt2cp2 8 8 2 or 3 pclkb 2 iclk 0008 c47ah rtc date capture register 2 rdaycp2 8 8 2 or 3 pclkb 2 iclk 0008 c47ah rtc bcnt3 capture register 2 bcnt3cp2 8 8 2 or 3 pclkb 2 iclk 0008 c47ch rtc month capture register 2 rmoncp2 8 8 2 or 3 pclkb 2 iclk 0008 c580h cmpb comparator b control register 1 cpbcnt1 8 8 2 or 3 pclkb 2 iclk 0008 c581h cmpb comparator b control register 2 cpbcnt2 8 8 2 or 3 pclkb 2 iclk 0008 c582h cmpb comparator b flag register cpbflg 8 8 2 or 3 pclkb 2 iclk 0008 c583h cmpb comparator b interrupt control register cpbint 8 8 2 or 3 pclkb 2 iclk 0008 c584h cmpb comparator b filter select register cpbf 8 8 2 or 3 pclkb 2 iclk 0008 c585h cmpb comparator b mode select register cpbmd 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (28 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 71 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 0008 c586h cmpb comparator b reference input voltage select register cpbref 8 8 2 or 3 pclkb 2 iclk 0008 c587h cmpb comparator b output control register cpbocr 8 8 2 or 3 pclkb 2 iclk 0008 c5a0h cmpb comparator b1 control register 1 cpb1cnt1 8 8 2 or 3 pclkb 2 iclk 0008 c5a1h cmpb comparator b1 control register 2 cpb1cnt2 8 8 2 or 3 pclkb 2 iclk 0008 c5a2h cmpb comparator b1 flag register cpb1flg 8 8 2 or 3 pclkb 2 iclk 0008 c5a3h cmpb comparator b1 interrupt control register cpb1int 8 8 2 or 3 pclkb 2 iclk 0008 c5a4h cmpb comparator b1 filter select register cpb1f 8 8 2 or 3 pclkb 2 iclk 0008 c5a5h cmpb comparator b1 mode select register cpb1md 8 8 2 or 3 pclkb 2 iclk 0008 c5a6h cmpb comparator b1 reference input voltage select register cpb1ref 8 8 2 or 3 pclkb 2 iclk 0008 c5a7h cmpb comparator b1 output control register cpb1ocr 8 8 2 or 3 pclkb 2 iclk 000a 0000h usb0 system configuration control register syscfg 16 16 3, 4 pclkb 2 iclk 000a 0004h usb0 system configuration status register 0 syssts0 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0008h usb0 device state control register 0 dvstctr0 16 16 9 pclkb or more rounded up to the nearest integer greater than 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0014h usb0 cfifo port register cfifo 16 16 3, 4 pclkb 2 iclk 000a 0018h usb0 d0fifo port register d0fifo 16 16 3, 4 pclkb 2 iclk 000a 001ch usb0 d1fifo port register d1fifo 16 16 3, 4 pclkb 2 iclk 000a 0020h usb0 cfifo port select register cfifosel 16 16 3, 4 pclkb 2 iclk 000a 0022h usb0 cfifo port control register cfifoctr 16 16 3, 4 pclkb 2 iclk 000a 0028h usb0 d0fifo port select register d0fifosel 16 16 3, 4 pclkb 2 iclk 000a 002ah usb0 d0fifo port control re gister d0fifoctr 16 16 3, 4 pclkb 2 iclk 000a 002ch usb0 d1fifo port select register d1fifosel 16 16 3, 4 pclkb 2 iclk 000a 002eh usb0 d1fifo port control re gister d1fifoctr 16 16 3, 4 pclkb 2 iclk 000a 0030h usb0 interrupt enable register 0 intenb0 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0032h usb0 interrupt enable register 1 intenb1 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0036h usb0 brdy interrupt enable register brdyenb 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0038h usb0 nrdy interrupt enable register nrdyenb 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 003ah usb0 bemp interrupt enable register bempenb 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 003ch usb0 sof output configuration register sofcfg 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0040h usb0 interrupt status register 0 intsts0 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0042h usb0 interrupt status register 1 intsts1 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0046h usb0 brdy interrupt status register brdysts 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0048h usb0 nrdy interrupt status register nrdysts 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 004ah usb0 bemp interrupt status register bempsts 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 004ch usb0 frame number register frmnum 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 table 4.1 list of i/o register s (address order) (29 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 72 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 0054h usb0 usb request type register usbreq 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0056h usb0 usb request value register usbval 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0058h usb0 usb request index register usbindx 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 005ah usb0 usb request length register usbleng 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 005ch usb0 dcp configuration register dcpcfg 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 005eh usb0 dcp maximum packet size register dcpmaxp 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0060h usb0 dcp control register dcpctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0064h usb0 pipe window select register pipesel 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0068h usb0 pipe configuration register pipecfg 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 006ch usb0 pipe maximum packet size register pipemaxp 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 006eh usb0 pipe cycle control register pipeperi 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0070h usb0 pipe1 control register pipe1ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0072h usb0 pipe2 control register pipe2ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0074h usb0 pipe3 control register pipe3ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0076h usb0 pipe4 control register pipe4ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0078h usb0 pipe5 control register pipe5ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 007ah usb0 pipe6 control register pipe6ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 007ch usb0 pipe7 control register pipe7ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 007eh usb0 pipe8 control register pipe8ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0080h usb0 pipe9 control register pipe9ctr 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0090h usb0 pipe1 transaction counter enable register pipe1tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0092h usb0 pipe1 transaction counter register pipe1trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0094h usb0 pipe2 transaction counter enable register pipe2tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0096h usb0 pipe2 transaction counter register pipe2trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 table 4.1 list of i/o register s (address order) (30 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 73 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 0098h usb0 pipe3 transaction counter enable register pipe3tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 009ah usb0 pipe3 transaction counter register pipe3trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 009ch usb0 pipe4 transaction counter enable register pipe4tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 009eh usb0 pipe4 transaction counter register pipe4trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00a0h usb0 pipe5 transaction counter enable register pipe5tre 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00a2h usb0 pipe5 transaction counter register pipe5trn 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00b0h usb0 bc control register 0 usbbcctrl0 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00cch usb0 usb module control register usbmc 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00d0h usb0 device address 0 configuration register devadd0 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00d2h usb0 device address 1 configuration register devadd1 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00d4h usb0 device address 2 configuration register devadd2 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00d6h usb0 device address 3 configuration register devadd3 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00d8h usb0 device address 4 configuration register devadd4 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 00dah usb0 device address 5 configuration register devadd5 16 16 9 pclkb or more frequency with 1 + 9 (frequency ratio of iclk/pclkb)* 2 000a 0900h ctsu ctsu control register 0 ctsucr0 8 8 2 or 3 pclkb 2 iclk 000a 0901h ctsu ctsu control register 1 ctsucr1 8 8 2 or 3 pclkb 2 iclk 000a 0902h ctsu ctsu synchronous noise reduction setting register ctsusdprs 8 8 2 or 3 pclkb 2 iclk 000a 0903h ctsu ctsu sensor stabilization wait control register ctsusst 8 8 2 or 3 pclkb 2 iclk 000a 0904h ctsu ctsu measurement channel register 0 ctsumch0 8 8 2 or 3 pclkb 2 iclk 000a 0905h ctsu ctsu measurement channel register 1 ctsumch1 8 8 2 or 3 pclkb 2 iclk 000a 0906h ctsu ctsu channel enable control register 0 ctsuchac0 8 8 2 or 3 pclkb 2 iclk 000a 0907h ctsu ctsu channel enable control register 1 ctsuchac1 8 8 2 or 3 pclkb 2 iclk 000a 0908h ctsu ctsu channel enable control register 2 ctsuchac2 8 8 2 or 3 pclkb 2 iclk 000a 0909h ctsu ctsu channel enable control register 3 ctsuchac3 8 8 2 or 3 pclkb 2 iclk 000a 090ah ctsu ctsu channel enable control register 4 ctsuchac4 8 8 2 or 3 pclkb 2 iclk 000a 090bh ctsu ctsu channel transmit/receive control register 0 ctsuchtrc0 8 8 2 or 3 pclkb 2 iclk 000a 090ch ctsu ctsu channel transmit/receive control register 1 ctsuchtrc1 8 8 2 or 3 pclkb 2 iclk 000a 090dh ctsu ctsu channel transmit/receive control register 2 ctsuchtrc2 8 8 2 or 3 pclkb 2 iclk 000a 090eh ctsu ctsu channel transmit/receive control register 3 ctsuchtrc3 8 8 2 or 3 pclkb 2 iclk 000a 090fh ctsu ctsu channel transmit/receive control register 4 ctsuchtrc4 8 8 2 or 3 pclkb 2 iclk 000a 0910h ctsu ctsu high-pass noise reduction control register ctsudclkc 8 8 2 or 3 pclkb 2 iclk 000a 0911h ctsu ctsu status register ctsust 8 8 2 or 3 pclkb 2 iclk 000a 0912h ctsu ctsu high-pass noise reduction spectrum diffusion control register ctsussc 16 16 2 or 3 pclkb 2 iclk 000a 0914h ctsu ctsu sensor offset register 0 ctsuso0 16 16 2 or 3 pclkb 2 iclk 000a 0916h ctsu ctsu sensor offset register 1 ctsuso1 16 16 2 or 3 pclkb 2 iclk 000a 0918h ctsu ctsu sensor counter ctsusc 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (31 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 74 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 091ah ctsu ctsu reference counter ctsurc 16 16 2 or 3 pclkb 2 iclk 000a 091ch ctsu ctsu error status register ctsuerrs 16 16 2 or 3 pclkb 2 iclk 000a 8300h can0 bit configuration register l cfgl 16 16 2 or 3 pclkb 2 iclk 000a 8302h can0 bit configuration register h cfgh 16 16 2 or 3 pclkb 2 iclk 000a 8304h can0 control register l ctrl 16 16 2 or 3 pclkb 2 iclk 000a 8306h can0 control register h ctrh 16 16 2 or 3 pclkb 2 iclk 000a 8308h can0 status register l stsl 16 16 2 or 3 pclkb 2 iclk 000a 830ah can0 status register h stsh 16 16 2 or 3 pclkb 2 iclk 000a 830ch can0 error flag register l erfll 16 16 2 or 3 pclkb 2 iclk 000a 830eh can0 error flag register h erflh 16 16 2 or 3 pclkb 2 iclk 000a 8322h can global configuration register l gcfgl 16 16 2 or 3 pclkb 2 iclk 000a 8324h can global configuration register h gcfgh 16 16 2 or 3 pclkb 2 iclk 000a 8326h can global control register l gctrl 16 16 2 or 3 pclkb 2 iclk 000a 8328h can global control register h gctrh 16 16 2 or 3 pclkb 2 iclk 000a 832ah can global status register gsts 16 16 2 or 3 pclkb 2 iclk 000a 832ch can global error flag register gerfll 8 8 2 or 3 pclkb 2 iclk 000a 832eh can timestamp register gtsc 16 16 2 or 3 pclkb 2 iclk 000a 8330h can receive rule number configuration register gaflcfg 16 16 2 or 3 pclkb 2 iclk 000a 8332h can receive buffer number configuration register rmnb 16 16 2 or 3 pclkb 2 iclk 000a 8334h can receive buffer receive complete flag register rmnd0 16 16 2 or 3 pclkb 2 iclk 000a 8338h can receive fifo control regi ster 0 rfcc0 16 16 2 or 3 pclkb 2 iclk 000a 833ah can receive fifo control regi ster 1 rfcc1 16 16 2 or 3 pclkb 2 iclk 000a 8340h can receive fifo status register 0 rfsts0 16 16 2 or 3 pclkb 2 iclk 000a 8342h can receive fifo status register 1 rfsts1 16 16 2 or 3 pclkb 2 iclk 000a 8348h can receive fifo pointer control register 0 rfpctr0 16 16 2 or 3 pclkb 2 iclk 000a 834ah can receive fifo pointer control register 1 rfpctr1 16 16 2 or 3 pclkb 2 iclk 000a 8350h can0 transmit/receive fifo control register 0l cfccl0 16 16 2 or 3 pclkb 2 iclk 000a 8352h can0 transmit/receive fifo control register 0h cfcch0 16 16 2 or 3 pclkb 2 iclk 000a 8358h can0 transmit/receive fifo status register 0 cfsts0 16 16 2 or 3 pclkb 2 iclk 000a 835ch can0 transmit/receive fifo pointer cont rol register 0 cfpctr0 16 16 2 or 3 pclkb 2 iclk 000a 8360h can receive fifo message lost status register rfmsts 8 8 2 or 3 pclkb 2 iclk 000a 8361h can0 transmit/receive fifo message lost status register cfmsts 8 8 2 or 3 pclkb 2 iclk 000a 8362h can receive fifo interrupt status register rfists 8 8 2 or 3 pclkb 2 iclk 000a 8363h can transmit/receive fifo receive interr upt status register cfists 8 8 2 or 3 pclkb 2 iclk 000a 8364h can0 transmit buffer control register 0 tmc0 8 8 2 or 3 pclkb 2 iclk 000a 8365h can0 transmit buffer control register 1 tmc1 8 8 2 or 3 pclkb 2 iclk 000a 8366h can0 transmit buffer control register 2 tmc2 8 8 2 or 3 pclkb 2 iclk 000a 8367h can0 transmit buffer control register 3 tmc3 8 8 2 or 3 pclkb 2 iclk 000a 836ch can0 transmit buffer status register 0 tmsts0 8 8 2 or 3 pclkb 2 iclk 000a 836dh can0 transmit buffer status register 1 tmsts1 8 8 2 or 3 pclkb 2 iclk 000a 836eh can0 transmit buffer status register 2 tmsts2 8 8 2 or 3 pclkb 2 iclk 000a 836fh can0 transmit buffer status register 3 tmsts3 8 8 2 or 3 pclkb 2 iclk 000a 8374h can0 transmit buffer transmit request status register tmtrsts 16 16 2 or 3 pclkb 2 iclk 000a 8376h can0 transmit buffer transmit complete status register tmtcsts 16 16 2 or 3 pclkb 2 iclk 000a 8378h can0 transmit buffer transmit abort status register tmtasts 16 16 2 or 3 pclkb 2 iclk 000a 837ah can0 transmit buffer interrupt enable register tmiec 16 16 2 or 3 pclkb 2 iclk 000a 837ch can0 transmit history buffer control register thlcc0 16 16 2 or 3 pclkb 2 iclk 000a 8380h can0 transmit history buffer status register thlsts0 16 16 2 or 3 pclkb 2 iclk 000a 8384h can0 transmit history buffer pointer control register thlpctr0 16 16 2 or 3 pclkb 2 iclk 000a 8388h can global transmit interrupt status register gtintsts 16 16 2 or 3 pclkb 2 iclk 000a 838ah can global ram window control register grwcr 16 16 2 or 3 pclkb 2 iclk 000a 838ch can global test configuration register gtstcfg 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (32 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 75 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 838eh can global test control register gtstctrl 16 16 2 or 3 pclkb 2 iclk 000a 8394h can global test protection unlock register glockk 16 16 2 or 3 pclkb 2 iclk 000a 83a0h can receive rule entry register 0al gaflidl0 16 16 2 or 3 pclkb 2 iclk 000a 83a0h can receive buffer register 0al rmidl0 16 16 2 or 3 pclkb 2 iclk 000a 83a2h can receive rule entry register 0ah gaflidh0 16 16 2 or 3 pclkb 2 iclk 000a 83a2h can receive buffer register 0ah rmidh0 16 16 2 or 3 pclkb 2 iclk 000a 83a4h can receive rule entry register 0bl gaflml0 16 16 2 or 3 pclkb 2 iclk 000a 83a4h can receive buffer register 0bl rmts0 16 16 2 or 3 pclkb 2 iclk 000a 83a6h can receive rule entry register 0bh gaflmh0 16 16 2 or 3 pclkb 2 iclk 000a 83a6h can receive buffer register 0bh rmptr0 16 16 2 or 3 pclkb 2 iclk 000a 83a8h can receive rule entry register 0cl gaflpl0 16 16 2 or 3 pclkb 2 iclk 000a 83a8h can receive buffer register 0cl rmdf00 16 16 2 or 3 pclkb 2 iclk 000a 83aah can receive rule entry register 0ch gaflph0 16 16 2 or 3 pclkb 2 iclk 000a 83aah can receive buffer register 0ch rmdf10 16 16 2 or 3 pclkb 2 iclk 000a 83ach can receive rule entry register 1al gaflidl1 16 16 2 or 3 pclkb 2 iclk 000a 83ach can receive buffer register 0dl rmdf20 16 16 2 or 3 pclkb 2 iclk 000a 83aeh can receive rule entry register 1ah gaflidh1 16 16 2 or 3 pclkb 2 iclk 000a 83aeh can receive buffer register 0dh rmdf30 16 16 2 or 3 pclkb 2 iclk 000a 83b0h can receive rule entry register 1bl gaflml1 16 16 2 or 3 pclkb 2 iclk 000a 83b0h can receive buffer register 1al rmidl1 16 16 2 or 3 pclkb 2 iclk 000a 83b2h can receive rule entry register 1bh gaflmh1 16 16 2 or 3 pclkb 2 iclk 000a 83b2h can receive buffer register 1ah rmidh1 16 16 2 or 3 pclkb 2 iclk 000a 83b4h can receive rule entry register 1cl gaflpl1 16 16 2 or 3 pclkb 2 iclk 000a 83b4h can receive buffer register 1bl rmts1 16 16 2 or 3 pclkb 2 iclk 000a 83b6h can receive rule entry register 1ch gaflph1 16 16 2 or 3 pclkb 2 iclk 000a 83b6h can receive buffer register 1bh rmptr1 16 16 2 or 3 pclkb 2 iclk 000a 83b8h can receive rule entry register 2al gaflidl2 16 16 2 or 3 pclkb 2 iclk 000a 83b8h can receive buffer register 1cl rmdf01 16 16 2 or 3 pclkb 2 iclk 000a 83bah can receive rule entry register 2ah gaflidh2 16 16 2 or 3 pclkb 2 iclk 000a 83bah can receive buffer register 1ch rmdf11 16 16 2 or 3 pclkb 2 iclk 000a 83bch can receive rule entry register 2bl gaflml2 16 16 2 or 3 pclkb 2 iclk 000a 83bch can receive buffer register 1dl rmdf21 16 16 2 or 3 pclkb 2 iclk 000a 83beh can receive rule entry register 2bh gaflmh2 16 16 2 or 3 pclkb 2 iclk 000a 83beh can receive buffer register 1dh rmdf31 16 16 2 or 3 pclkb 2 iclk 000a 83c0h can receive rule entry register 2cl gaflpl2 16 16 2 or 3 pclkb 2 iclk 000a 83c0h can receive buffer register 2al rmidl2 16 16 2 or 3 pclkb 2 iclk 000a 83c2h can receive rule entry register 2ch gaflph2 16 16 2 or 3 pclkb 2 iclk 000a 83c2h can receive buffer register 2ah rmidh2 16 16 2 or 3 pclkb 2 iclk 000a 83c4h can receive rule entry register 3al gaflidl3 16 16 2 or 3 pclkb 2 iclk 000a 83c4h can receive buffer register 2bl rmts2 16 16 2 or 3 pclkb 2 iclk 000a 83c6h can receive rule entry register 3ah gaflidh3 16 16 2 or 3 pclkb 2 iclk 000a 83c6h can receive buffer register 2bh rmptr2 16 16 2 or 3 pclkb 2 iclk 000a 83c8h can receive rule entry register 3bl gaflml3 16 16 2 or 3 pclkb 2 iclk 000a 83c8h can receive buffer register 2cl rmdf02 16 16 2 or 3 pclkb 2 iclk 000a 83cah can receive rule entry register 3bh gaflmh3 16 16 2 or 3 pclkb 2 iclk 000a 83cah can receive buffer register 2ch rmdf12 16 16 2 or 3 pclkb 2 iclk 000a 83cch can receive rule entry register 3cl gaflpl3 16 16 2 or 3 pclkb 2 iclk 000a 83cch can receive buffer register 2dl rmdf22 16 16 2 or 3 pclkb 2 iclk 000a 83ceh can receive rule entry register 3ch gaflph3 16 16 2 or 3 pclkb 2 iclk 000a 83ceh can receive buffer register 2dh rmdf32 16 16 2 or 3 pclkb 2 iclk 000a 83d0h can receive rule entry register 4al gaflidl4 16 16 2 or 3 pclkb 2 iclk 000a 83d0h can receive buffer register 3al rmidl3 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (33 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 76 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 83d2h can receive rule entry register 4ah gaflidh4 16 16 2 or 3 pclkb 2 iclk 000a 83d2h can receive buffer register 3ah rmidh3 16 16 2 or 3 pclkb 2 iclk 000a 83d4h can receive rule entry register 4bl gaflml4 16 16 2 or 3 pclkb 2 iclk 000a 83d4h can receive buffer register 3bl rmts3 16 16 2 or 3 pclkb 2 iclk 000a 83d6h can receive rule entry register 4bh gaflmh4 16 16 2 or 3 pclkb 2 iclk 000a 83d6h can receive buffer register 3bh rmptr3 16 16 2 or 3 pclkb 2 iclk 000a 83d8h can receive rule entry register 4cl gaflpl4 16 16 2 or 3 pclkb 2 iclk 000a 83d8h can receive buffer register 3cl rmdf03 16 16 2 or 3 pclkb 2 iclk 000a 83dah can receive rule entry register 4ch gaflph4 16 16 2 or 3 pclkb 2 iclk 000a 83dah can receive buffer register 3ch rmdf13 16 16 2 or 3 pclkb 2 iclk 000a 83dch can receive rule entry register 5al gaflidl5 16 16 2 or 3 pclkb 2 iclk 000a 83dch can receive buffer register 3dl rmdf23 16 16 2 or 3 pclkb 2 iclk 000a 83deh can receive rule entry register 5ah gaflidh5 16 16 2 or 3 pclkb 2 iclk 000a 83deh can receive buffer register 3dh rmdf33 16 16 2 or 3 pclkb 2 iclk 000a 83e0h can receive rule entry register 5bl gaflml5 16 16 2 or 3 pclkb 2 iclk 000a 83e0h can receive buffer register 4al rmidl4 16 16 2 or 3 pclkb 2 iclk 000a 83e2h can receive rule entry register 5bh gaflmh5 16 16 2 or 3 pclkb 2 iclk 000a 83e2h can receive buffer register 4ah rmidh4 16 16 2 or 3 pclkb 2 iclk 000a 83e4h can receive rule entry register 5cl gaflpl5 16 16 2 or 3 pclkb 2 iclk 000a 83e4h can receive buffer register 4bl rmts4 16 16 2 or 3 pclkb 2 iclk 000a 83e6h can receive rule entry register 5ch gaflph5 16 16 2 or 3 pclkb 2 iclk 000a 83e6h can receive buffer register 4bh rmptr4 16 16 2 or 3 pclkb 2 iclk 000a 83e8h can receive rule entry register 6al gaflidl6 16 16 2 or 3 pclkb 2 iclk 000a 83e8h can receive buffer register 4cl rmdf04 16 16 2 or 3 pclkb 2 iclk 000a 83eah can receive rule entry register 6ah gaflidh6 16 16 2 or 3 pclkb 2 iclk 000a 83eah can receive buffer register 4ch rmdf14 16 16 2 or 3 pclkb 2 iclk 000a 83ech can receive rule entry register 6bl gaflml6 16 16 2 or 3 pclkb 2 iclk 000a 83ech can receive buffer register 4dl rmdf24 16 16 2 or 3 pclkb 2 iclk 000a 83eeh can receive rule entry register 6bh gaflmh6 16 16 2 or 3 pclkb 2 iclk 000a 83eeh can receive buffer register 4dh rmdf34 16 16 2 or 3 pclkb 2 iclk 000a 83f0h can receive rule entry register 6cl gaflpl6 16 16 2 or 3 pclkb 2 iclk 000a 83f0h can receive buffer register 5al rmidl5 16 16 2 or 3 pclkb 2 iclk 000a 83f2h can receive rule entry register 6ch gaflph6 16 16 2 or 3 pclkb 2 iclk 000a 83f2h can receive buffer register 5ah rmidh5 16 16 2 or 3 pclkb 2 iclk 000a 83f4h can receive rule entry register 7al gaflidl7 16 16 2 or 3 pclkb 2 iclk 000a 83f4h can receive buffer register 5bl rmts5 16 16 2 or 3 pclkb 2 iclk 000a 83f6h can receive rule entry register 7ah gaflidh7 16 16 2 or 3 pclkb 2 iclk 000a 83f6h can receive buffer register 5bh rmptr5 16 16 2 or 3 pclkb 2 iclk 000a 83f8h can receive rule entry register 7bl gaflml7 16 16 2 or 3 pclkb 2 iclk 000a 83f8h can receive buffer register 5cl rmdf05 16 16 2 or 3 pclkb 2 iclk 000a 83fah can receive rule entry register 7bh gaflmh7 16 16 2 or 3 pclkb 2 iclk 000a 83fah can receive buffer register 5ch rmdf15 16 16 2 or 3 pclkb 2 iclk 000a 83fch can receive rule entry register 7cl gaflpl7 16 16 2 or 3 pclkb 2 iclk 000a 83fch can receive buffer register 5dl rmdf25 16 16 2 or 3 pclkb 2 iclk 000a 83feh can receive rule entry register 7ch gaflph7 16 16 2 or 3 pclkb 2 iclk 000a 83feh can receive buffer register 5dh rmdf35 16 16 2 or 3 pclkb 2 iclk 000a 8400h can receive rule entry register 8al gaflidl8 16 16 2 or 3 pclkb 2 iclk 000a 8400h can receive buffer register 6al rmidl6 16 16 2 or 3 pclkb 2 iclk 000a 8402h can receive rule entry register 8ah gaflidh8 16 16 2 or 3 pclkb 2 iclk 000a 8402h can receive buffer register 6ah rmidh6 16 16 2 or 3 pclkb 2 iclk 000a 8404h can receive rule entry register 8bl gaflml8 16 16 2 or 3 pclkb 2 iclk 000a 8404h can receive buffer register 6bl rmts6 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (34 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 77 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 8406h can receive rule entry register 8bh gaflmh8 16 16 2 or 3 pclkb 2 iclk 000a 8406h can receive buffer register 6bh rmptr6 16 16 2 or 3 pclkb 2 iclk 000a 8408h can receive rule entry register 8cl gaflpl8 16 16 2 or 3 pclkb 2 iclk 000a 8408h can receive buffer register 6cl rmdf06 16 16 2 or 3 pclkb 2 iclk 000a 840ah can receive rule entry register 8ch gaflph8 16 16 2 or 3 pclkb 2 iclk 000a 840ah can receive buffer register 6ch rmdf16 16 16 2 or 3 pclkb 2 iclk 000a 840ch can receive rule entry register 9al gaflidl9 16 16 2 or 3 pclkb 2 iclk 000a 840ch can receive buffer register 6dl rmdf26 16 16 2 or 3 pclkb 2 iclk 000a 840eh can receive rule entry register 9ah gaflidh9 16 16 2 or 3 pclkb 2 iclk 000a 840eh can receive buffer register 6dh rmdf36 16 16 2 or 3 pclkb 2 iclk 000a 8410h can receive rule entry register 9bl gaflml9 16 16 2 or 3 pclkb 2 iclk 000a 8410h can receive buffer register 7al rmidl7 16 16 2 or 3 pclkb 2 iclk 000a 8412h can receive rule entry register 9bh gaflmh9 16 16 2 or 3 pclkb 2 iclk 000a 8412h can receive buffer register 7ah rmidh7 16 16 2 or 3 pclkb 2 iclk 000a 8414h can receive rule entry register 9cl gaflpl9 16 16 2 or 3 pclkb 2 iclk 000a 8414h can receive buffer register 7bl rmts7 16 16 2 or 3 pclkb 2 iclk 000a 8416h can receive rule entry register 9ch gaflph9 16 16 2 or 3 pclkb 2 iclk 000a 8416h can receive buffer register 7bh rmptr7 16 16 2 or 3 pclkb 2 iclk 000a 8418h can receive rule entry register 10al gaflidl10 16 16 2 or 3 pclkb 2 iclk 000a 8418h can receive buffer register 7cl rmdf07 16 16 2 or 3 pclkb 2 iclk 000a 841ah can receive rule entry register 10ah gaflidh10 16 16 2 or 3 pclkb 2 iclk 000a 841ah can receive buffer register 7ch rmdf17 16 16 2 or 3 pclkb 2 iclk 000a 841ch can receive rule entry register 10bl gaflml10 16 16 2 or 3 pclkb 2 iclk 000a 841ch can receive buffer register 7dl rmdf27 16 16 2 or 3 pclkb 2 iclk 000a 841eh can receive rule entry register 10bh gaflmh10 16 16 2 or 3 pclkb 2 iclk 000a 841eh can receive buffer register 7dh rmdf37 16 16 2 or 3 pclkb 2 iclk 000a 8420h can receive rule entry register 10cl gaflpl10 16 16 2 or 3 pclkb 2 iclk 000a 8420h can receive buffer register 8al rmidl8 16 16 2 or 3 pclkb 2 iclk 000a 8422h can receive rule entry register 10ch gaflph10 16 16 2 or 3 pclkb 2 iclk 000a 8422h can receive buffer register 8ah rmidh8 16 16 2 or 3 pclkb 2 iclk 000a 8424h can receive rule entry register 11al gaflidl11 16 16 2 or 3 pclkb 2 iclk 000a 8424h can receive buffer register 8bl rmts8 16 16 2 or 3 pclkb 2 iclk 000a 8426h can receive rule entry register 11ah gaflidh11 16 16 2 or 3 pclkb 2 iclk 000a 8426h can receive buffer register 8bh rmptr8 16 16 2 or 3 pclkb 2 iclk 000a 8428h can receive rule entry register 11bl gaflml11 16 16 2 or 3 pclkb 2 iclk 000a 8428h can receive buffer register 8cl rmdf08 16 16 2 or 3 pclkb 2 iclk 000a 842ah can receive rule entry register 11bh gaflmh11 16 16 2 or 3 pclkb 2 iclk 000a 842ah can receive buffer register 8ch rmdf18 16 16 2 or 3 pclkb 2 iclk 000a 842ch can receive rule entry register 11cl gaflpl11 16 16 2 or 3 pclkb 2 iclk 000a 842ch can receive buffer register 8dl rmdf28 16 16 2 or 3 pclkb 2 iclk 000a 842eh can receive rule entry register 11ch gaflph11 16 16 2 or 3 pclkb 2 iclk 000a 842eh can receive buffer register 8dh rmdf38 16 16 2 or 3 pclkb 2 iclk 000a 8430h can receive rule entry register 12al gaflidl12 16 16 2 or 3 pclkb 2 iclk 000a 8430h can receive buffer register 9al rmidl9 16 16 2 or 3 pclkb 2 iclk 000a 8432h can receive rule entry register 12ah gaflidh12 16 16 2 or 3 pclkb 2 iclk 000a 8432h can receive buffer register 9ah rmidh9 16 16 2 or 3 pclkb 2 iclk 000a 8434h can receive rule entry register 12bl gaflml12 16 16 2 or 3 pclkb 2 iclk 000a 8434h can receive buffer register 9bl rmts9 16 16 2 or 3 pclkb 2 iclk 000a 8436h can receive rule entry register 12bh gaflmh12 16 16 2 or 3 pclkb 2 iclk 000a 8436h can receive buffer register 9bh rmptr9 16 16 2 or 3 pclkb 2 iclk 000a 8438h can receive rule entry register 12cl gaflpl12 16 16 2 or 3 pclkb 2 iclk 000a 8438h can receive buffer register 9cl rmdf09 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (35 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 78 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 843ah can receive rule entry register 12ch gaflph12 16 16 2 or 3 pclkb 2 iclk 000a 843ah can receive buffer register 9ch rmdf19 16 16 2 or 3 pclkb 2 iclk 000a 843ch can receive rule entry register 13al gaflidl13 16 16 2 or 3 pclkb 2 iclk 000a 843ch can receive buffer register 9dl rmdf29 16 16 2 or 3 pclkb 2 iclk 000a 843eh can receive rule entry register 13ah gaflidh13 16 16 2 or 3 pclkb 2 iclk 000a 843eh can receive buffer register 9dh rmdf39 16 16 2 or 3 pclkb 2 iclk 000a 8440h can receive rule entry register 13bl gaflml13 16 16 2 or 3 pclkb 2 iclk 000a 8440h can receive buffer register 10al rmidl10 16 16 2 or 3 pclkb 2 iclk 000a 8442h can receive rule entry register 13bh gaflmh13 16 16 2 or 3 pclkb 2 iclk 000a 8442h can receive buffer register 10ah rmidh10 16 16 2 or 3 pclkb 2 iclk 000a 8444h can receive rule entry register 13cl gaflpl13 16 16 2 or 3 pclkb 2 iclk 000a 8444h can receive buffer register 10bl rmts10 16 16 2 or 3 pclkb 2 iclk 000a 8446h can receive rule entry register 13ch gaflph13 16 16 2 or 3 pclkb 2 iclk 000a 8446h can receive buffer register 10bh rmptr10 16 16 2 or 3 pclkb 2 iclk 000a 8448h can receive rule entry register 14al gaflidl14 16 16 2 or 3 pclkb 2 iclk 000a 8448h can receive buffer register 10cl rmdf010 16 16 2 or 3 pclkb 2 iclk 000a 844ah can receive rule entry register 14ah gaflidh14 16 16 2 or 3 pclkb 2 iclk 000a 844ah can receive buffer register 10ch rmdf110 16 16 2 or 3 pclkb 2 iclk 000a 844ch can receive rule entry register 14bl gaflml14 16 16 2 or 3 pclkb 2 iclk 000a 844ch can receive buffer register 10dl rmdf210 16 16 2 or 3 pclkb 2 iclk 000a 844eh can receive rule entry register 14bh gaflmh14 16 16 2 or 3 pclkb 2 iclk 000a 844eh can receive buffer register 10dh rmdf310 16 16 2 or 3 pclkb 2 iclk 000a 8450h can receive rule entry register 14cl gaflpl14 16 16 2 or 3 pclkb 2 iclk 000a 8450h can receive buffer register 11al rmidl11 16 16 2 or 3 pclkb 2 iclk 000a 8452h can receive rule entry register 14ch gaflph14 16 16 2 or 3 pclkb 2 iclk 000a 8452h can receive buffer register 11ah rmidh11 16 16 2 or 3 pclkb 2 iclk 000a 8454h can receive rule entry register 15al gaflidl15 16 16 2 or 3 pclkb 2 iclk 000a 8454h can receive buffer register 11bl rmts11 16 16 2 or 3 pclkb 2 iclk 000a 8456h can receive rule entry register 15ah gaflidh15 16 16 2 or 3 pclkb 2 iclk 000a 8456h can receive buffer register 11bh rmptr11 16 16 2 or 3 pclkb 2 iclk 000a 8458h can receive rule entry register 15bl gaflml15 16 16 2 or 3 pclkb 2 iclk 000a 8458h can receive buffer register 11cl rmdf011 16 16 2 or 3 pclkb 2 iclk 000a 845ah can receive rule entry register 15bh gaflmh15 16 16 2 or 3 pclkb 2 iclk 000a 845ah can receive buffer register 11ch rmdf111 16 16 2 or 3 pclkb 2 iclk 000a 845ch can receive rule entry register 15cl gaflpl15 16 16 2 or 3 pclkb 2 iclk 000a 845ch can receive buffer register 11dl rmdf211 16 16 2 or 3 pclkb 2 iclk 000a 845eh can receive rule entry register 15ch gaflph15 16 16 2 or 3 pclkb 2 iclk 000a 845eh can receive buffer register 11dh rmdf311 16 16 2 or 3 pclkb 2 iclk 000a 8460h can receive buffer register 12al rmidl12 16 16 2 or 3 pclkb 2 iclk 000a 8462h can receive buffer register 12ah rmidh12 16 16 2 or 3 pclkb 2 iclk 000a 8464h can receive buffer register 12bl rmts12 16 16 2 or 3 pclkb 2 iclk 000a 8466h can receive buffer register 12bh rmptr12 16 16 2 or 3 pclkb 2 iclk 000a 8468h can receive buffer register 12cl rmdf012 16 16 2 or 3 pclkb 2 iclk 000a 846ah can receive buffer register 12ch rmdf112 16 16 2 or 3 pclkb 2 iclk 000a 846ch can receive buffer register 12dl rmdf212 16 16 2 or 3 pclkb 2 iclk 000a 846eh can receive buffer register 12dh rmdf312 16 16 2 or 3 pclkb 2 iclk 000a 8470h can receive buffer register 13al rmidl13 16 16 2 or 3 pclkb 2 iclk 000a 8472h can receive buffer register 13ah rmidh13 16 16 2 or 3 pclkb 2 iclk 000a 8474h can receive buffer register 13bl rmts13 16 16 2 or 3 pclkb 2 iclk 000a 8476h can receive buffer register 13bh rmptr13 16 16 2 or 3 pclkb 2 iclk 000a 8478h can receive buffer register 13cl rmdf013 16 16 2 or 3 pclkb 2 iclk 000a 847ah can receive buffer register 13ch rmdf113 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (36 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 79 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 847ch can receive buffer register 13dl rmdf213 16 16 2 or 3 pclkb 2 iclk 000a 847eh can receive buffer register 13dh rmdf313 16 16 2 or 3 pclkb 2 iclk 000a 8480h can receive buffer register 14al rmidl14 16 16 2 or 3 pclkb 2 iclk 000a 8482h can receive buffer register 14ah rmidh14 16 16 2 or 3 pclkb 2 iclk 000a 8484h can receive buffer register 14bl rmts14 16 16 2 or 3 pclkb 2 iclk 000a 8486h can receive buffer register 14bh rmptr14 16 16 2 or 3 pclkb 2 iclk 000a 8488h can receive buffer register 14cl rmdf014 16 16 2 or 3 pclkb 2 iclk 000a 848ah can receive buffer register 14ch rmdf114 16 16 2 or 3 pclkb 2 iclk 000a 848ch can receive buffer register 14dl rmdf214 16 16 2 or 3 pclkb 2 iclk 000a 848eh can receive buffer register 14dh rmdf314 16 16 2 or 3 pclkb 2 iclk 000a 8490h can receive buffer register 15al rmidl15 16 16 2 or 3 pclkb 2 iclk 000a 8492h can receive buffer register 15ah rmidh15 16 16 2 or 3 pclkb 2 iclk 000a 8494h can receive buffer register 15bl rmts15 16 16 2 or 3 pclkb 2 iclk 000a 8496h can receive buffer register 15bh rmptr15 16 16 2 or 3 pclkb 2 iclk 000a 8498h can receive buffer register 15cl rmdf015 16 16 2 or 3 pclkb 2 iclk 000a 849ah can receive buffer register 15ch rmdf115 16 16 2 or 3 pclkb 2 iclk 000a 849ch can receive buffer register 15dl rmdf215 16 16 2 or 3 pclkb 2 iclk 000a 849eh can receive buffer register 15dh rmdf315 16 16 2 or 3 pclkb 2 iclk 000a 8580h to 000a 859fh can ram test register 0 to 15 rpgacc0 to 15 16 16 2 or 3 pclkb 2 iclk 000a 85a0h can receive fifo access register 0al rfidl0 16 16 2 or 3 pclkb 2 iclk 000a 85a0h can ram test register 16 rpgacc16 16 16 2 or 3 pclkb 2 iclk 000a 85a2h can receive fifo access register 0ah rfidh0 16 16 2 or 3 pclkb 2 iclk 000a 85a2h can ram test register 17 rpgacc17 16 16 2 or 3 pclkb 2 iclk 000a 85a4h can receive fifo access register 0bl rfts0 16 16 2 or 3 pclkb 2 iclk 000a 85a4h can ram test register 18 rpgacc18 16 16 2 or 3 pclkb 2 iclk 000a 85a6h can receive fifo access register 0bh rfptr0 16 16 2 or 3 pclkb 2 iclk 000a 85a6h can ram test register 19 rpgacc19 16 16 2 or 3 pclkb 2 iclk 000a 85a8h can receive fifo access register 0cl rfdf00 16 16 2 or 3 pclkb 2 iclk 000a 85a8h can ram test register 20 rpgacc20 16 16 2 or 3 pclkb 2 iclk 000a 85aah can receive fifo access register 0ch rfdf10 16 16 2 or 3 pclkb 2 iclk 000a 85aah can ram test register 21 rpgacc21 16 16 2 or 3 pclkb 2 iclk 000a 85ach can receive fifo access register 0dl rfdf20 16 16 2 or 3 pclkb 2 iclk 000a 85ach can ram test register 22 rpgacc22 16 16 2 or 3 pclkb 2 iclk 000a 85aeh can receive fifo access register 0dh rfdf30 16 16 2 or 3 pclkb 2 iclk 000a 85aeh can ram test register 23 rpgacc23 16 16 2 or 3 pclkb 2 iclk 000a 85b0h can receive fifo access register 1al rfidl1 16 16 2 or 3 pclkb 2 iclk 000a 85b0h can ram test register 24 rpgacc24 16 16 2 or 3 pclkb 2 iclk 000a 85b2h can receive fifo access register 1ah rfidh1 16 16 2 or 3 pclkb 2 iclk 000a 85b2h can ram test register 25 rpgacc25 16 16 2 or 3 pclkb 2 iclk 000a 85b4h can receive fifo access register 1bl rfts1 16 16 2 or 3 pclkb 2 iclk 000a 85b4h can ram test register 26 rpgacc26 16 16 2 or 3 pclkb 2 iclk 000a 85b6h can receive fifo access register 1bh rfptr1 16 16 2 or 3 pclkb 2 iclk 000a 85b6h can ram test register 27 rpgacc27 16 16 2 or 3 pclkb 2 iclk 000a 85b8h can receive fifo access register 1cl rfdf01 16 16 2 or 3 pclkb 2 iclk 000a 85b8h can ram test register 28 rpgacc28 16 16 2 or 3 pclkb 2 iclk 000a 85bah can receive fifo access register 1ch rfdf11 16 16 2 or 3 pclkb 2 iclk 000a 85bah can ram test register 29 rpgacc29 16 16 2 or 3 pclkb 2 iclk 000a 85bch can receive fifo access register 1dl rfdf21 16 16 2 or 3 pclkb 2 iclk 000a 85bch can ram test register 30 rpgacc30 16 16 2 or 3 pclkb 2 iclk 000a 85beh can receive fifo access register 1dh rfdf31 16 16 2 or 3 pclkb 2 iclk 000a 85beh can ram test register 31 rpgacc31 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (37 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 80 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 85c0h to 000a 85deh can ram test register 32 to 47 rpgacc32 to 47 16 16 2 or 3 pclkb 2 iclk 000a 85e0h can0 transmit/receive fifo access register 0al cfidl0 16 16 2 or 3 pclkb 2 iclk 000a 85e0h can ram test register 48 rpgacc48 16 16 2 or 3 pclkb 2 iclk 000a 85e2h can0 transmit/receive fifo access register 0ah cfidh0 16 16 2 or 3 pclkb 2 iclk 000a 85e2h can ram test register 49 rpgacc49 16 16 2 or 3 pclkb 2 iclk 000a 85e4h can0 transmit/receive fifo access register 0bl cfts0 16 16 2 or 3 pclkb 2 iclk 000a 85e4h can ram test register 50 rpgacc50 16 16 2 or 3 pclkb 2 iclk 000a 85e6h can0 transmit/receive fifo access re gister 0bh cfptr0 16 16 2 or 3 pclkb 2 iclk 000a 85e6h can ram test register 51 rpgacc51 16 16 2 or 3 pclkb 2 iclk 000a 85e8h can0 transmit/receive fifo access re gister 0cl cfdf00 16 16 2 or 3 pclkb 2 iclk 000a 85e8h can ram test register 52 rpgacc52 16 16 2 or 3 pclkb 2 iclk 000a 85eah can0 transmit/receive fifo access re gister 0ch cfdf10 16 16 2 or 3 pclkb 2 iclk 000a 85eah can ram test register 53 rpgacc53 16 16 2 or 3 pclkb 2 iclk 000a 85ech can0 transmit/receive fifo access re gister 0dl cfdf20 16 16 2 or 3 pclkb 2 iclk 000a 85ech can ram test register 54 rpgacc54 16 16 2 or 3 pclkb 2 iclk 000a 85eeh can0 transmit/receive fifo access re gister 0dh cfdf30 16 16 2 or 3 pclkb 2 iclk 000a 85eeh can ram test register 55 rpgacc55 16 16 2 or 3 pclkb 2 iclk 000a 85f0h to 000a 85feh can ram test register 56 to 63 rpgacc56 to 63 16 16 2 or 3 pclkb 2 iclk 000a 8600h can0 transmit buffer register 0al tmidl0 16 16 2 or 3 pclkb 2 iclk 000a 8600h can ram test register 64 rpgacc64 16 16 2 or 3 pclkb 2 iclk 000a 8602h can0 transmit buffer register 0ah tmidh0 16 16 2 or 3 pclkb 2 iclk 000a 8602h can ram test register 65 rpgacc65 16 16 2 or 3 pclkb 2 iclk 000a 8604h can ram test register 66 rpgacc66 16 16 2 or 3 pclkb 2 iclk 000a 8606h can0 transmit buffer register 0bh tmptr0 16 16 2 or 3 pclkb 2 iclk 000a 8606h can ram test register 67 rpgacc67 16 16 2 or 3 pclkb 2 iclk 000a 8608h can0 transmit buffer register 0cl tmdf00 16 16 2 or 3 pclkb 2 iclk 000a 8608h can ram test register 68 rpgacc68 16 16 2 or 3 pclkb 2 iclk 000a 860ah can0 transmit buffer register 0ch tmdf10 16 16 2 or 3 pclkb 2 iclk 000a 860ah can ram test register 69 rpgacc69 16 16 2 or 3 pclkb 2 iclk 000a 860ch can0 transmit buffer register 0dl tmdf20 16 16 2 or 3 pclkb 2 iclk 000a 860ch can ram test register 70 rpgacc70 16 16 2 or 3 pclkb 2 iclk 000a 860eh can0 transmit buffer register 0dh tmdf30 16 16 2 or 3 pclkb 2 iclk 000a 860eh can ram test register 71 rpgacc71 16 16 2 or 3 pclkb 2 iclk 000a 8610h can0 transmit buffer register 1al tmidl1 16 16 2 or 3 pclkb 2 iclk 000a 8610h can ram test register 72 rpgacc72 16 16 2 or 3 pclkb 2 iclk 000a 8612h can0 transmit buffer register 1ah tmidh1 16 16 2 or 3 pclkb 2 iclk 000a 8612h can ram test register 73 rpgacc73 16 16 2 or 3 pclkb 2 iclk 000a 8614h can ram test register 74 rpgacc74 16 16 2 or 3 pclkb 2 iclk 000a 8616h can0 transmit buffer register 1bh tmptr1 16 16 2 or 3 pclkb 2 iclk 000a 8616h can ram test register 75 rpgacc75 16 16 2 or 3 pclkb 2 iclk 000a 8618h can0 transmit buffer register 1cl tmdf01 16 16 2 or 3 pclkb 2 iclk 000a 8618h can ram test register 76 rpgacc76 16 16 2 or 3 pclkb 2 iclk 000a 861ah can0 transmit buffer register 1ch tmdf11 16 16 2 or 3 pclkb 2 iclk 000a 861ah can ram test register 77 rpgacc77 16 16 2 or 3 pclkb 2 iclk 000a 861ch can0 transmit buffer register 1dl tmdf21 16 16 2 or 3 pclkb 2 iclk 000a 861ch can ram test register 78 rpgacc78 16 16 2 or 3 pclkb 2 iclk 000a 861eh can0 transmit buffer register 1dh tmdf31 16 16 2 or 3 pclkb 2 iclk 000a 861eh can ram test register 79 rpgacc79 16 16 2 or 3 pclkb 2 iclk 000a 8620h can0 transmit buffer register 2al tmidl2 16 16 2 or 3 pclkb 2 iclk 000a 8620h can ram test register 80 rpgacc80 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (38 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 81 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000a 8622h can0 transmit buffer register 2ah tmidh2 16 16 2 or 3 pclkb 2 iclk 000a 8622h can ram test register 81 rpgacc81 16 16 2 or 3 pclkb 2 iclk 000a 8624h can ram test register 82 rpgacc82 16 16 2 or 3 pclkb 2 iclk 000a 8626h can0 transmit buffer register 2bh tmptr2 16 16 2 or 3 pclkb 2 iclk 000a 8626h can ram test register 83 rpgacc83 16 16 2 or 3 pclkb 2 iclk 000a 8628h can0 transmit buffer register 2cl tmdf02 16 16 2 or 3 pclkb 2 iclk 000a 8628h can ram test register 84 rpgacc84 16 16 2 or 3 pclkb 2 iclk 000a 862ah can0 transmit buffer register 2ch tmdf12 16 16 2 or 3 pclkb 2 iclk 000a 862ah can ram test register 85 rpgacc85 16 16 2 or 3 pclkb 2 iclk 000a 862ch can0 transmit buffer register 2dl tmdf22 16 16 2 or 3 pclkb 2 iclk 000a 862ch can ram test register 86 rpgacc86 16 16 2 or 3 pclkb 2 iclk 000a 862eh can0 transmit buffer register 2dh tmdf32 16 16 2 or 3 pclkb 2 iclk 000a 862eh can ram test register 87 rpgacc87 16 16 2 or 3 pclkb 2 iclk 000a 8630h can0 transmit buffer register 3al tmidl3 16 16 2 or 3 pclkb 2 iclk 000a 8630h can ram test register 88 rpgacc88 16 16 2 or 3 pclkb 2 iclk 000a 8632h can0 transmit buffer register 3ah tmidh3 16 16 2 or 3 pclkb 2 iclk 000a 8632h can ram test register 89 rpgacc89 16 16 2 or 3 pclkb 2 iclk 000a 8634h can ram test register 90 rpgacc90 16 16 2 or 3 pclkb 2 iclk 000a 8636h can0 transmit buffer register 3bh tmptr3 16 16 2 or 3 pclkb 2 iclk 000a 8636h can ram test register 91 rpgacc91 16 16 2 or 3 pclkb 2 iclk 000a 8638h can0 transmit buffer register 3cl tmdf03 16 16 2 or 3 pclkb 2 iclk 000a 8638h can ram test register 92 rpgacc92 16 16 2 or 3 pclkb 2 iclk 000a 863ah can0 transmit buffer register 3ch tmdf13 16 16 2 or 3 pclkb 2 iclk 000a 863ah can ram test register 93 rpgacc93 16 16 2 or 3 pclkb 2 iclk 000a 863ch can0 transmit buffer register 3dl tmdf23 16 16 2 or 3 pclkb 2 iclk 000a 863ch can ram test register 94 rpgacc94 16 16 2 or 3 pclkb 2 iclk 000a 863eh can0 transmit buffer register 3dh tmdf33 16 16 2 or 3 pclkb 2 iclk 000a 863eh can ram test register 95 rpgacc95 16 16 2 or 3 pclkb 2 iclk 000a 8640h to 000a 867eh can ram test register 96 to 127 rpgacc96 to 127 16 16 2 or 3 pclkb 2 iclk 000a 8680h can0 transmit history buffer acce ss register thlacc0 16 16 2 or 3 pclkb 2 iclk 000d 0a00h mtu3 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 000d 0a01h mtu4 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 000d 0a02h mtu3 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 000d 0a03h mtu4 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 000d 0a04h mtu3 timer i/o control register h tiorh 8 8 2 or 3 pclkb 2 iclk 000d 0a05h mtu3 timer i/o control register l tiorl 8 8 2 or 3 pclkb 2 iclk 000d 0a06h mtu4 timer i/o control register h tiorh 8 8 2 or 3 pclkb 2 iclk 000d 0a07h mtu4 timer i/o control register l tiorl 8 8 2 or 3 pclkb 2 iclk 000d 0a08h mtu3 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 000d 0a09h mtu4 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 000d 0a0ah mtu timer output master enable register toer 8 8 2 or 3 pclkb 2 iclk 000d 0a0dh mtu timer gate control register tgcr 8 8 2 or 3 pclkb 2 iclk 000d 0a0eh mtu timer output control register 1 tocr1 8 8 2 or 3 pclkb 2 iclk 000d 0a0fh mtu timer output control register 2 tocr2 8 8 2 or 3 pclkb 2 iclk 000d 0a10h mtu3 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 000d 0a12h mtu4 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 000d 0a14h mtu timer cycle data register tcdr 16 16 2 or 3 pclkb 2 iclk 000d 0a16h mtu timer dead time data register tddr 16 16 2 or 3 pclkb 2 iclk 000d 0a18h mtu3 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 000d 0a1ah mtu3 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 000d 0a1ch mtu4 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (39 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 82 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000d 0a1eh mtu4 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 000d 0a20h mtu timer subcounters tcnts 16 16 2 or 3 pclkb 2 iclk 000d 0a22h mtu timer cycle buffer register tcbr 16 16 2 or 3 pclkb 2 iclk 000d 0a24h mtu3 timer general register c tgrc 16 16 2 or 3 pclkb 2 iclk 000d 0a26h mtu3 timer general register d tgrd 16 16 2 or 3 pclkb 2 iclk 000d 0a28h mtu4 timer general register c tgrc 16 16 2 or 3 pclkb 2 iclk 000d 0a2ah mtu4 timer general register d tgrd 16 16 2 or 3 pclkb 2 iclk 000d 0a2ch mtu3 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 000d 0a2dh mtu4 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 000d 0a30h mtu timer interrupt skipping set register titcr 8 8 2 or 3 pclkb 2 iclk 000d 0a31h mtu timer interrupt skipping counters titcnt 8 8 2 or 3 pclkb 2 iclk 000d 0a32h mtu timer buffer transfer set register tbter 8 8 2 or 3 pclkb 2 iclk 000d 0a34h mtu timer dead time enable register tder 8 8 2 or 3 pclkb 2 iclk 000d 0a36h mtu timer output level buffer register tolbr 8 8 2 or 3 pclkb 2 iclk 000d 0a38h mtu3 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 2 iclk 000d 0a39h mtu4 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 2 iclk 000d 0a40h mtu4 timer a/d converter start request control register tadcr 16 16 2 or 3 pclkb 2 iclk 000d 0a44h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 2 or 3 pclkb 2 iclk 000d 0a46h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 2 or 3 pclkb 2 iclk 000d 0a48h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2 or 3 pclkb 2 iclk 000d 0a4ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2 or 3 pclkb 2 iclk 000d 0a60h mtu timer waveform control register twcr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a80h mtu timer start register tstr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a81h mtu timer synchronous register tsyr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a84h mtu timer read/write enable register trwer 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a90h mtu0 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a91h mtu1 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a92h mtu2 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a93h mtu3 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a94h mtu4 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0a95h mtu5 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 2 iclk 000d 0b00h mtu0 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 000d 0b01h mtu0 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 000d 0b02h mtu0 timer i/o control register h tiorh 8 8 2 or 3 pclkb 2 iclk 000d 0b03h mtu0 timer i/o control register l tiorl 8 8 2 or 3 pclkb 2 iclk 000d 0b04h mtu0 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 000d 0b05h mtu0 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 000d 0b06h mtu0 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 000d 0b08h mtu0 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 000d 0b0ah mtu0 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 000d 0b0ch mtu0 timer general register c tgrc 16 16 2 or 3 pclkb 2 iclk 000d 0b0eh mtu0 timer general register d tgrd 16 16 2 or 3 pclkb 2 iclk 000d 0b20h mtu0 timer general register e tgre 16 16 2 or 3 pclkb 2 iclk 000d 0b22h mtu0 timer general register f tgrf 16 16 2 or 3 pclkb 2 iclk 000d 0b24h mtu0 timer interrupt enable register 2 tier2 8 8 2 or 3 pclkb 2 iclk 000d 0b26h mtu0 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 2 iclk 000d 0b80h mtu1 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 000d 0b81h mtu1 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 000d 0b82h mtu1 timer i/o control register tior 8 8 2 or 3 pclkb 2 iclk 000d 0b84h mtu1 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 000d 0b85h mtu1 timer status register tsr 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (40 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 83 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers 000d 0b86h mtu1 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 000d 0b88h mtu1 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 000d 0b8ah mtu1 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 000d 0b90h mtu1 timer input capture control register ticcr 8 8 2 or 3 pclkb 2 iclk 000d 0c00h mtu2 timer control register tcr 8 8 2 or 3 pclkb 2 iclk 000d 0c01h mtu2 timer mode register tmdr 8 8 2 or 3 pclkb 2 iclk 000d 0c02h mtu2 timer i/o control register tior 8 8 2 or 3 pclkb 2 iclk 000d 0c04h mtu2 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 000d 0c05h mtu2 timer status register tsr 8 8 2 or 3 pclkb 2 iclk 000d 0c06h mtu2 timer counter tcnt 16 16 2 or 3 pclkb 2 iclk 000d 0c08h mtu2 timer general register a tgra 16 16 2 or 3 pclkb 2 iclk 000d 0c0ah mtu2 timer general register b tgrb 16 16 2 or 3 pclkb 2 iclk 000d 0c80h mtu5 timer counter u tcntu 16 16 2 or 3 pclkb 2 iclk 000d 0c82h mtu5 timer general register u tgru 16 16 2 or 3 pclkb 2 iclk 000d 0c84h mtu5 timer control register u tcru 8 8 2 or 3 pclkb 2 iclk 000d 0c86h mtu5 timer i/o control register u tioru 8 8 2 or 3 pclkb 2 iclk 000d 0c90h mtu5 timer counter v tcntv 16 16 2 or 3 pclkb 2 iclk 000d 0c92h mtu5 timer general register v tgrv 16 16 2 or 3 pclkb 2 iclk 000d 0c94h mtu5 timer control register v tcrv 8 8 2 or 3 pclkb 2 iclk 000d 0c96h mtu5 timer i/o control register v tiorv 8 8 2 or 3 pclkb 2 iclk 000d 0ca0h mtu5 timer counter w tcntw 16 16 2 or 3 pclkb 2 iclk 000d 0ca2h mtu5 timer general register w tgrw 16 16 2 or 3 pclkb 2 iclk 000d 0ca4h mtu5 timer control register w tcrw 8 8 2 or 3 pclkb 2 iclk 000d 0ca6h mtu5 timer i/o control register w tiorw 8 8 2 or 3 pclkb 2 iclk 000d 0cb2h mtu5 timer interrupt enable register tier 8 8 2 or 3 pclkb 2 iclk 000d 0cb4h mtu5 timer start register tstr 8 8 2 or 3 pclkb 2 iclk 000d 0cb6h mtu5 timer compare match clear register tcntcmpclr 8 8 2 or 3 pclkb 2 iclk 007f c090h flash e2 dataflash control register dflctl 8 8 2 or 3 pclkb 2 iclk 007f c0ach tempsa temperature sensor calibration data register l tscdrl 8 8 2 or 3 pclkb 2 iclk 007f c0adh tempsa temperature sensor calibration data register h tscdrh 8 8 2 or 3 pclkb 2 iclk 007f c100h flash flash p/e mode control register fpmcr 8 8 2 or 3 pclkb 2 iclk 007f c104h flash flash area select register fasr 8 8 2 or 3 pclkb 2 iclk 007f c108h flash flash processing start address register l fsarl 16 16 2 or 3 pclkb 2 iclk 007f c110h flash flash processing start address register h fsarh 16 16 2 or 3 pclkb 2 iclk 007f c114h flash flash control register fcr 8 8 2 or 3 pclkb 2 iclk 007f c118h flash flash processing end address register l fearl 16 16 2 or 3 pclkb 2 iclk 007f c120h flash flash processing end address register h fearh 16 16 2 or 3 pclkb 2 iclk 007f c124h flash flash reset register fresetr 8 8 2 or 3 pclkb 2 iclk 007f c12ch flash flash status register 1 fstatr1 8 8 2 or 3 pclkb 2 iclk 007f c130h flash flash write buffer register 0 fwb0 16 16 2 or 3 pclkb 2 iclk 007f c138h flash flash write buffer register 1 fwb1 16 16 2 or 3 pclkb 2 iclk 007f c140h flash flash write buffer register 2 fwb2 16 16 2 or 3 pclkb 2 iclk 007f c144h flash flash write buffer register 3 fwb3 16 16 2 or 3 pclkb 2 iclk 007f c180h flash protection unlock register fpr 8 8 2 or 3 pclkb 2 iclk 007f c184h flash protection unlock status register fpsr 8 8 2 or 3 pclkb 2 iclk 007f c1c0h flash flash start-up setting monitor register fscmr 16 16 2 or 3 pclkb 2 iclk 007f c1c8h flash flash access window start address monitor register fawsmr 16 16 2 or 3 pclkb 2 iclk 007f c1d0h flash flash access window end address monitor register fawemr 16 16 2 or 3 pclkb 2 iclk 007f c1d8h flash flash initial setting register fisr 8 8 2 or 3 pclkb 2 iclk 007f c1dch flash flash extra area control register fexcr 8 8 2 or 3 pclkb 2 iclk 007f c1e0h flash flash error address monitor register l feaml 16 16 2 or 3 pclkb 2 iclk 007f c1e8h flash flash error address monitor register h feamh 8 8 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (41 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 84 of 177 oct 30, 2015 rx230 group, rx231 group 4. i/o registers note 1. odd addresses cannot be accessed in 16-bit units. table 26.4 lists register allocation for 16-bit access in the user?s m anual: hardware. note 2. when the register is accessed while the usb is operating, a delay may be generated in accessing. 007f c1f0h flash flash status register 0 fstatr0 8 8 2 or 3 pclkb 2 iclk 007f c350h flashcon st unique id register 0 uidr0 32 32 2 or 3 pclkb 2 iclk 007f c354h flashcon st unique id register 1 uidr1 32 32 2 or 3 pclkb 2 iclk 007f c358h flashcon st unique id register 2 uidr2 32 32 2 or 3 pclkb 2 iclk 007f c35ch flashcon st unique id register 3 uidr3 32 32 2 or 3 pclkb 2 iclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 or 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (42 / 42) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk r01ds0261ej0110 rev.1.10 page 85 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the mcu may be caused if absolute maximum ratings are exceeded. to preclude any malfunctions due to noise interference, insert capacitors with high frequency characteristics between the vcc and vss pins, between the avcc0 and avss0 pins, between the vcc_usb and vss_usb pins, between the vrefh0 and vrefl0 pins, and between the vrefh and vref l pins. place capacitors of about 0.1 f as close as possible to every power supply pin and use the shortest and heaviest possible traces. connect the vcl pin to a vss pin via a 4.7 f capacitor. the capacitor must be placed close to the pin. for details, refer to section 5.15.1, connecting vcl capacitor and bypass capacitors. do not input signals or an i/o pull-up power supply to ports other than 5-v tolerant ports while the device is not powered. the current injection that results from input of such a signal or i/o pull-up may cause malfunction and the abnormal current th at passes in the device at this time may cause degradation of internal elements. even if ?0.3 to +6.5 v is input to 5-v tolerant p orts, it will not cause problems such as damage to the mcu. note 1. ports 12, 13, 16, 17, 30, 31, 32, and b5 are 5 v tolerant. note 2. the upper limit of operating temperature is 85c or 105c, depending on the product. for details, refer to section 1.2, list of products. table 5.1 absolute maximum ratings conditions: vss = avss0 = vrefl0 = vrefl= vss_usb = 0 v item symbol value unit power supply voltage vcc, vcc_usb ?0.3 to +6.5 v vbatt power supply voltage vbatt ?0.3 to +6.5 v input voltage ports for 5 v tolerant* 1 v in ?0.3 to +6.5 v p03, p05, p40 to p47 ?0.3 to avcc0 +0.3 ports other than above ?0.3 to vcc +0.3 reference power supply voltage vrefh0 ?0.3 to avcc0 +0.3 v vrefh analog power supply voltage avcc0 ?0.3 to +6.5 v analog input voltage when an000 to an007 are used v an ?0.3 to avcc0 +0.3 v when an016 to an031 are used ?0.3 to vcc +0.3 operating temperature* 2 t opr ?40 to +85 ?40 to +105 c storage temperature t stg ?55 to +125 c
r01ds0261ej0110 rev.1.10 page 86 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. use avcc0 and vcc under the following conditions: avcc0 and vcc can be set individually within the operating range when vcc 2.0 v avcc0 = vcc when vcc ? 2.0 v note 2. when powering on the vcc and avcc0 pins, power them on at the same time or the vcc pin first and then the avcc0 pin. table 5.2 recommended operating voltage conditions item symbol conditions min. typ. max. unit power supply voltages vcc *1, *2 when usb is not used 1.8 ? 5.5 v when usb is used when usb regulator is not used 3.0 ? 3.6 when usb is used when usb regulator is used 4.0 ? 5.5 vss ? 0 ? usb power supply voltages vcc_usb when usb regulator is not used ? vcc ? v vss_usb ? 0 ? vbatt power supply voltage vbatt 1.8 ? 5.5 v analog power supply voltages avcc0 *1, *2 1.8 ? 5.5 v avss0 ? 0 ? vrefh0 1.8 ? avcc0 vrefl0 ? 0 ? vrefh 1.8 ? avcc0 vrefl ? 0 ?
r01ds0261ej0110 rev.1.10 page 87 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.2 dc characteristics table 5.3 dc characteristics (1) conditions: 2.7 v vcc = vcc_usb 5.5 v, 2.7 v avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage riic input pin (except for smbus, 5 v tolerant) v ih vcc 0.7 ? 5.8 v ports 12, 13, 16, 17, port b5 (5 v tolerant) vcc 0.8 ? 5.8 ports 14 to 15, ports 20 to 27, ports 33 to 37, ports 50 to 55, ports a0 to a7, ports b0 to b4, b6, b7 ports c0 to c7, ports d0 to d7, ports e0 to e7, port j3, ports 30 to 32 (when time capture event input is not selected), res vcc 0.8 ? vcc + 0.3 ports 03, 05, 07, ports 40 to 47 avcc0 0.8 ? avcc0 + 0.3 ports 30 to 32 (when time capture event input is selected) when vcc is supplied vcc 0.8 ? vcc + 0.3 when vbatt is supplied vbatt 0.8 ? vbatt + 0.3 ports 03, 05, 07, ports 40 to 47 v il ?0.3 ? avcc0 0.2 riic input pin (except for smbus) ?0.3 ? vcc 0.3 other than riic input pin or ports 30 to 32 ?0.3 ? vcc 0.2 ports 30 to 32 (when time capture event input is selected) when vcc is supplied ?0.3 ? vcc 0.3 when vbatt is supplied ?0.3 ? vbatt 0.3 ports 03, 05, 07, ports 40 to 47 ?v t avcc0 0.1 ? ? riic input pin (except for smbus) vcc 0.05 ? ? ports 12, 13, 16, 17, port b5 vcc 0.05 ? ? other than riic input pin vcc 0.1 ? ? input level voltage (except for schmitt trigger input pins) md v ih vcc 0.9 ? vcc + 0.3 v extal (external clock input) vcc 0.8 ? vcc + 0.3 riic input pin (smbus) 2.1 ? vcc + 0.3 md v il ?0.3 ? vcc 0.1 extal (external clock input) ?0.3 ? vcc 0.2 riic input pin (smbus) ?0.3 ? 0.8
r01ds0261ej0110 rev.1.10 page 88 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics table 5.4 dc characteristics (2) conditions: 1.8 v vcc = vcc_usb < 2.7 v, 1.8 v avcc0 < 2.7 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage ports 12, 13, 16, 17, port b5 (5 v tolerant) v ih vcc 0.8 ? 5.8 v ports 14 to 15, ports 20 to 27, ports 30 to 37, ports 50 to 55, ports a0 to a7, ports b0 to b4, b6, b7, ports c0 to c7, ports d0 to d7, ports e0 to e7, port j3, res vcc 0.8 ? vcc + 0.3 ports 03, 05, 07, ports 40 to 47 avcc0 0.8 ? avcc0 + 0.3 ports 03, 05, 07, ports 40 to 47 v il ?0.3 ? avcc0 0.2 ports other than above ?0.3 ? vcc 0.2 ports 03, 05, 07, ports 40 to 47 ?v t avcc0 0.01 ? ? ports other than above vcc 0.01 ? ? input level voltage (except for schmitt trigger input pins) md v ih vcc 0.9 ? vcc + 0.3 v extal (external clock input) vcc 0.8 ? vcc + 0.3 md v il ?0.3 ? vcc 0.1 extal (external clock input) ?0.3 ? vcc 0.2 table 5.5 dc characteristics (3) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions input leakage current res#, md, port 35 ? i in ? ??1.0 av in = 0 v, vcc three-state leakage current (off-state) ports for 5 v tolerant ? i tsi ? ??1.0 av in = 0 v, 5.8v ports except for 5 v tolerant ? ? 0.2 av in = 0 v, vcc input capacitance all input pins (except for port 35, usb0_dm, usb0_dp) c in ? ? 15 pf v in = 0 mv, f = 1 mhz, t a = 25c port 35, usb0_dm, usb0_dp ? ? 30 table 5.6 dc characteristics (4) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions input pull-up resistor all ports (except for port 35) r u 10 20 50 k ? v in = 0 v
r01ds0261ej0110 rev.1.10 page 89 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics table 5.7 dc characteristics (5) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol typ. * 4 max. unit test conditions supply current * 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 54 mhz i cc 6.5 ? ma iclk = 32 mhz 4.1 ? iclk = 16 mhz 2.9 ? iclk = 8 mhz 2.2 ? iclk = 4 mhz 1.9 ? all peripheral operation: normal iclk = 54 mhz* 11 26.5 ? iclk = 32 mhz* 3 21.0 ? iclk = 16 mhz* 3 11.8 ? iclk = 8 mhz* 3 6.6 ? iclk = 4 mhz* 3 4.2 ? all peripheral operation: max. iclk = 54 mhz* 11 ? 53.3 iclk = 32 mhz* 3 ? 40.8 increase during security function operation pclkb = 32 mhz ? 2 sleep mode no peripheral operation* 2 iclk = 54 mhz 3.5 ? iclk = 32 mhz 2.4 ? iclk = 16 mhz 1.9 ? iclk = 8 mhz 1.6 ? iclk = 4 mhz 1.5 ? all peripheral operation: normal iclk = 54 mhz* 11 13.4 ? iclk = 32 mhz* 3 12.5 ? iclk = 16 mhz* 3 7.3 ? iclk = 8 mhz* 3 4.6 ? iclk = 4 mhz* 3 3.3 ? deep sleep mode no peripheral operation* 2 iclk = 54 mhz 2.3 ? iclk = 32 mhz 1.5 ? iclk = 16 mhz 1.3 ? iclk = 8 mhz 1.2 ? iclk = 4 mhz 1.1 ? all peripheral operation: normal iclk = 54 mhz* 11 10.6 ? iclk = 32 mhz* 3 9.9 ? iclk = 16 mhz* 3 5.9 ? iclk = 8 mhz* 3 3.8 ? iclk = 4 mhz* 3 2.7 ? increase during bgo operation* 5 2.5 ? middle-speed operating mode normal operating mode no peripheral operation* 6 iclk = 12 mhz i cc 2.7 ? ma iclk = 8 mhz 1.8 ? iclk = 4 mhz 1.4 ? iclk = 1 mhz 1.1 ? all peripheral operation: normal* 7 iclk = 12 mhz 9.6 ? iclk = 8 mhz 6.2 ? iclk = 4 mhz 3.8 ? iclk = 1 mhz 2.3 ?
r01ds0261ej0110 rev.1.10 page 90 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. supply current values do not include the output charge/disc harge current from all pins. the values apply when internal p ull-up moss are in the off state. note 2. clock supply to the peripheral func tions is stopped. this does not include bgo oper ation. the clock source is pll. bclk, fclk, and pclk are set to divided by 64. note 3. clocks are supplied to the peripheral functions. this does not include bgo operati on. the clock source is pll. bclk, fcl k, and pclk are the same frequency as that of iclk. note 4. values when vcc is 3.3 v. note 5. this is the increase when data is programmed to or er ased from the rom or e2 dataflash during program execution. note 6. clock supply to the peripheral func tions is stopped. the clock s ource is pll when iclk is 12 mhz and hoco for other case s. bclk, fclk, and pclk are set to divided by 64. note 7. clocks are supplied to the peripheral functions. the clock source is pll when iclk is 12 mhz and hoco for other cases. bclk, fclk, and pclk are the same frequency of that of the iclk. note 8. clock supply to the peripheral func tions is stopped. the clock s ource is the sub oscillati on circuit. bclk, fclk, and pc lk are set to divided by 64. note 9. clocks are supplied to the peripheral functions. the clock source is the sub oscillation ci rcuit. bclk, fclk, and pclk a re the same frequency as that of iclk. note 10. this is the value when the mstpcra.mstpa17 (12-bit a/d converter module stop bit) is in the module stop state. note 11. clocks are supplied to the peripheral functions. this does not include bgo operati on. the clock source is pll. bclk, fc lk, and pclkb are set to divided by 2 and pclka and pclkd are the same frequency as that of iclk. supply current middle-speed operating mode normal operating mode all peripheral operation: max.* 7 iclk = 12 mhz i cc ? 16.7 ma sleep mode no peripheral operation* 6 iclk = 12 mhz 1.9 ? iclk = 8 mhz 1.2 ? iclk = 4 mhz 1.1 ? iclk = 1 mhz 1.0 ? all peripheral operation: normal* 7 iclk = 12 mhz 6.1 ? iclk = 8 mhz 4.4 ? iclk = 4 mhz 3.0 ? iclk = 1 mhz 2.0 ? deep sleep mode no peripheral operation* 6 iclk = 12 mhz 1.6 ? iclk = 8 mhz 1.0 ? iclk = 4 mhz 0.9 ? iclk = 1 mhz 0.8 ? all peripheral operation: normal* 7 iclk = 12 mhz 5.1 ? iclk = 8 mhz 3.7 ? iclk = 4 mhz 2.6 ? iclk = 1 mhz 1.8 ? increase during bgo operation* 5 2.5 ? low-speed operating mode normal operating mode no peripheral operation* 8 iclk = 32 khz i cc 5.2 ? a all peripheral operation: normal * 9, * 10 iclk = 32 khz 22.3 ? all peripheral operation: max.* 9, * 10 iclk = 32 khz ? 74.4 sleep mode no peripheral operation* 8 iclk = 32 khz 3.0 ? all peripheral operation: normal* 9 iclk = 32 khz 13.1 ? deep sleep mode no peripheral operation* 8 iclk = 32 khz 2.4 ? all peripheral operation: normal* 9 iclk = 32 khz 10.5 ? item symbol typ. * 4 max. unit test conditions
r01ds0261ej0110 rev.1.10 page 91 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.1 voltage dependency in high-speed operating mode (reference data) 2.0 2.5 3.0 3.5 4.0 4.5 6.0 5.0 5.5 1.5 vcc (v) ta = 105c, iclk = 54mhz *2 ta = 105c, iclk = 32mhz *2 ta = 25c, iclk = 54mhz *1 ta = 25c, iclk = 32mhz *1 ta = 105c, iclk = 16mhz *2 ta = 105c, iclk = 8mhz *2 ta = 25c, iclk = 16mhz *1 ta = 105c, iclk = 4mhz *2 ta = 25c, iclk = 8mhz *1 ta = 25c, iclk = 4mhz *1 50 40 30 20 10 0 icc (ma) 60 ta = 105c, iclk = 54mhz *2 ta = 25c, iclk = 54mhz *1 ta = 25c, iclk = 32mhz *1 ta = 105c, iclk = 32mhz *2 ta = 25c, iclk = 16mhz *1 ta = 105c, iclk = 16mhz *2 ta = 25c, iclk = 8mhz *1 ta = 105c, iclk = 8mhz *2 ta = 25c, iclk = 4mhz *1 ta = 105c, iclk = 4mhz *2 note 1. all peripheral operations except any bgo operat ion are operating normally. indicates the average of the typical samples through actual measurement during product evaluation. note 2. all peripheral operations except any bgo operati on are operating at maximum. indicates the average of the upper-limit samples through actual measurement during product evaluation.
r01ds0261ej0110 rev.1.10 page 92 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.2 voltage dependency in middle-speed operating mode (reference data) 2.0 2.5 3.0 3.5 4.0 4.5 6.0 5.0 5.5 1.5 vcc (v) ta = 105c, iclk = 12mhz *2 ta = 25c, iclk = 12mhz *1 ta = 25c, iclk = 8mhz *1 ta = 25c, iclk = 1mhz *1 ta = 25c, iclk = 4mhz *1 20 10 0 icc (ma) ta = 105c, iclk = 8mhz *2 ta = 105c, iclk = 4mhz *2 ta = 105c, iclk = 1mhz *2 ta = 105c, iclk = 12mhz *2 ta = 25c, iclk = 12mhz *1 ta = 25c, iclk = 8mhz *1 ta = 105c, iclk = 8mhz *2 ta = 25c, iclk = 4mhz *1 ta = 105c, iclk = 4mhz *2 ta = 25c, iclk = 1mhz *1 ta = 105c, iclk = 1mhz *2 note 1. all peripheral operations except any bgo operation are operating normally. indicates the average of the typical samples through actual measurement during product evaluation. note 2. all peripheral operations except any bgo operation are operating at maximum. indicates the average of the upper-limit samples through actual m easurement during product evaluation.
r01ds0261ej0110 rev.1.10 page 93 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.3 voltage dependency in low-speed operating mode (reference data) 2.0 2.5 3.0 3.5 4.0 4.5 6.0 5.0 5.5 1.5 50 40 30 20 10 0 icc ( ? a) 60 70 vcc (v) ta = 105c, iclk = 32.768khz *2 ta = 25c, iclk = 32.768khz *1 ta = 105c, iclk = 32.768khz *2 ta = 25c, iclk = 32.768khz *1 note 1. all peripheral operations except any bgo operation are operating normally. indicates the average of the typical samples through actual measurement during product evaluation. note 2. all peripheral operations except any bgo operation are operating at maximum. indicates the average of the upper-limit samples through actual me asurement during product evaluation.
r01ds0261ej0110 rev.1.10 page 94 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 2. the iwdt, lvd, and cmpb are stopped. note 3. when vcc is 3.3 v. note 4. this increment incl udes the oscill ation circuit. figure 5.4 voltage dependency in software standby mode (reference data) table 5.8 dc characteristics (6) conditions: 1.8 v vcc= vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 t a = 25c i cc 0.8 3.7 a t a = 55c 1.2 4.3 t a = 85c 3.5 18.6 t a = 105c 7.9 45.2 increment for iwdt operation 0.4 ? increment for lpt operation 0.4 ? use iwdt -dedicated on-chip oscillator for clock source increment for rtc operation* 4 0.4 ? rcr3.rtcdv[2:0] set to low drive capacity 1.2 ? rcr3.rtcdv[2:0] set to normal drive capacity ta = 105c * 2 ta = 105c *1 ta = 85c *2 ta = 85c *1 ta = 55c *2 ta = 25c *2 ta = 55c *1 ta = 25c *1 ta = 105c *2 ta = 105c *1 ta = 85c *2 ta = 85c *1 ta = 55c *2 ta = 55c *1 ta = 25c *1 ta = 25c *2 2 2.5 3 3.5 4 4.5 6 5 5.5 1.5 vcc (v) 10 icc (a) 1 0.1 100 note 1. indicates the average of the typical samples through actual measurement during product evaluation . note 2. indicates the average of the upper-limit samples through actual measurement during product evaluation.
r01ds0261ej0110 rev.1.10 page 95 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.5 temperature dependency in software standby mode (reference data) note 1. supply current values do not include output charge/discharge current from all pins. the values appl y when internal pull- up moss are in the off state. table 5.9 dc characteristics (7) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 rtc operation when vcc is off t a = 25c i cc 0.8 ? a vbatt = 2.0 v rcr3.rtcdv[2:0] set to low drive capacity t a = 55c 0.9 ? t a = 85c 1.0 ? t a = 105c 1.2 ? t a = 25c 0.9 ? vbatt = 3.3 v rcr3.rtcdv[2:0] set to low drive capacity t a = 55c 1.0 ? t a = 85c 1.1 ? t a = 105c 1.3 ? t a = 25c 1.5 ? vbatt = 2.0 v rcr3.rtcdv[2:0] set to normal drive capacity t a = 55c 1.8 ? t a = 85c 2.1 ? t a = 105c 2.4 ? t a = 25c 1.6 ? vbatt = 3.3 v rcr3.rtcdv[2:0] set to normal drive capacity t a = 55c 1.9 ? t a = 85c 2.2 ? t a = 105c 2.5 ? -40 -20 020406080 100 0.1 1 10 100 icc (a) ta (c) average value of the tested upper-limit samples during product evaluation. average value of the tested middle samples during product evaluation.
r01ds0261ej0110 rev.1.10 page 96 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.6 temperature dependency of rtc operation with vcc off (reference data) note: please contact a renesas electronics sales office for info rmation on the derating of the g-version product. derating is th e systematic reduction of l oad to improve reliability. note 1. total power dissipated by the entire chip (including output currents) table 5.10 dc characteristics (8) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v item symbol min. typ. max. unit test conditions permissible total power consumption* 1 pd ? ? 350 mw d-version product permissible total power consumption* 1 pd ? ? 130 mw g-version product 10 1 0 icc (a) -40 -20 0 20 40 60 80 100 120 ta (c) low drive capacity *1 normal drive capacity *1 low drive capacity *1 normal drive capacity *1 note 1. indicates the average of the typical samples through actual measurement during product evaluation .
r01ds0261ej0110 rev.1.10 page 97 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. the value of the d/a converter is the value of the power supply current including the reference current. note 2. current consumed only by the usb module. note 3. includes the current supplied from t he pull-up resistor of the usb0_dp pin to the pull-down resistor of the host device, in addition to the current consumed by this mcu during the suspended state. note 4. current consumed by the power supplies (vcc and vcc_usb). note 5. current consumed only by the comparator b module. note 6. current consumed by the power supply (vcc). note 7. when vcc = avcc0 = vcc_usb = 3.3 v. table 5.11 dc characteristics (9) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ.* 7 max. unit test conditions analog power supply current during a/d conversion (at high-speed conversion) i avcc ?0.71.7ma during a/d conversion (in low-current mode) ? 0.6 1.0 during d/a conversion (per channel)* 1 ?0.40.8 waiting for a/d and d/a conversion (all units) ? ? 0.4 a reference power supply current during a/d conversion (at high-speed conversion) i refh0 ? 25 150 a waiting for a/d conversion (all units) ? ? 60 na during d/a conversion (per channel) i refh ? 50 100 a waiting for d/a conversion (all units) ? ? 100 na lvd1, 2 per channel i lvd ?0.15? a temperature sensor* 6 ?i temp ?75? a comparator b operating current* 6 window mode i cmp * 5 ? 12.5 28.6 a comparator high-speed mode (per channel) ? 3.2 16.2 a comparator low-speed mode (per channel) ? 1.7 4.4 a ctsu operating current when sleep mode base clock frequency: 2mhz pin capacitance: 50pf i ctsu ? 150 ? a usb operating current* 4 during usb communication operation under the following settings and conditions ? host controller operation is set to full-speed mode bulk out transfer (64 bytes) 1, bulk in transfer (64 bytes) 1 ? connect peripheral devices via a 1-meter usb cable from the usb port. i usbh * 2 ?4.3 (vcc) 0.9 (vcc_usb) ?ma during usb communication operation under the following settings and conditions ? function controller operation is set to full-speed mode bulk out transfer (64 bytes) 1, bulk in transfer (64 bytes) 1 ? connect the host device via a 1-meter usb cable from the usb port. i usbf * 2 ?3.6 (vcc) 1.1 (vcc_usb) ?ma during suspended state under the following setting and conditions ? function controller operation is set to full-speed mode (pull up the usb0_dp pin) ? software standby mode ? connect the host device via a 1-meter usb cable from the usb port. i susp * 3 ?0.35 (vcc) 170 (vcc_usb) ? a table 5.12 dc characteristics (10) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions ram standby voltage v ram 1.8 ? ? v
r01ds0261ej0110 rev.1.10 page 98 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. when ofs1.(faststup, lvdas) bits are 11b. note 2. when ofs1.(faststup, lvdas) bits are 01b. note 3. when ofs1.lvdas bit is 0. note 4. turn on the power supply voltage according to the normal startup rising gradient because t he settings in the ofs1 regist er are not read in boot mode. figure 5.7 ripple waveform note: the recommended capacitance is 4.7 f. variations in connected capacitor s should be within the above range. table 5.13 dc characteristics (11) conditions: 0 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions power-on vcc rising gradient at normal startup* 1 srvcc 0.02 ? 20 ms/v during fast startup time* 2 0.02 ? 2 voltage monitoring 0 reset enabled at startup* 3, * 4 0.02 ? ? table 5.14 dc characteristics (12) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c the ripple voltage must meet the allowable ripple frequency f r (vcc) within the range between the vcc upper limit and lower limit. when vcc change exceeds vcc 10%, the allowable voltage change rising/falling gradient dt/dvcc must be met. item symbol min. typ. max. unit test conditions allowable ripple frequency f r (vcc) ? ? 10 khz figure 5.7 v r (vcc) vcc 0.2 ? ? 1 mhz figure 5.7 v r (vcc) vcc 0.08 ? ? 10 mhz figure 5.7 v r (vcc) vcc 0.06 allowable voltage change rising/falling gradient dt/dvcc 1.0 ? ? ms/v when vcc change exceeds vcc 10% table 5.15 dc characteristics (13) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions permissible error of vcl pin external capacitance c vcl 1.4 4.7 7.0 f v r(vcc) vcc 1 / f r(vcc)
r01ds0261ej0110 rev.1.10 page 99 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: do not exceed the permissible total supply current. table 5.16 permissible output currents (1) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +85c item symbol max. unit permissible output low current (average value per pin) ports 40 to 47, ports 03, 05, 07, port 36, 37 i ol 4.0 ma ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current (maximum value per pin) ports 40 to 47, ports 03, 05, 07, ports 36, 37 4.0 ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current total of ports 40 to 47, ports 03, 05, 07 ? i ol 40 total of ports 12 to 17, ports 20 to 27, ports 30 to 37, port pj3 40 total of ports 50 to 55, ports c0 to c7, ports b0 to b7 40 total of ports e0 to e7, ports a0 to a7, ports d0 to d4 40 total of all output pins 80 permissible output high current (average value per pin) ports 40 to 47, ports 03, 05, 07, ports 36, 37 i oh ?4.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current (maximum value per pin) ports 40 to 47, ports 03, 05, 07, ports 36, 37 ?4.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current total of ports 40 to 47, ports 03, 05, 07 ? i oh ?40 total of ports 12 to 17, ports 20 to 27, ports 30 to 37, port pj3 ?40 total of ports 50 to 55, ports c0 to c7, ports b0 to b7 ?40 total of ports e0 to e7, ports a0 to a7, ports d0 to d4 ?40 total of all output pins ?80
r01ds0261ej0110 rev.1.10 page 100 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: do not exceed the permissible total supply current. table 5.17 permissible output currents (2) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol max. unit permissible output low current (average value per pin) ports 40 to 47, ports 03, 05, 07, port 36, 37 i ol 4.0 ma ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current (maximum value per pin) ports 40 to 47, ports 03, 05, 07, ports 36, 37 4.0 ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current total of ports 40 to 47, ports 03, 05, 07 ? i ol 30 total of ports 12 to 17, ports 20 to 27, ports 30 to 37, port pj3 30 total of ports 50 to 55, ports c0 to c7, ports b0 to b7 30 total of ports e0 to e7, ports a0 to a7, ports d0 to d4 30 total of all output pins 60 permissible output high current (average value per pin) ports 40 to 47, ports 03, 05, 07, ports 36, 37 i oh ?4.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current (maximum value per pin) ports 40 to 47, ports 03, 05, 07, ports 36, 37 ?4.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current total of ports 40 to 47, ports 03, 05, 07 ? i oh ?30 total of ports 12 to 17, ports 20 to 27, ports 30 to 37, port pj3 ?30 total of ports 50 to 55, ports c0 to c7, ports b0 to b7 ?30 total of ports e0 to e7, ports a0 to a7, ports d0 to d4 ?30 total of all output pins ?60
r01ds0261ej0110 rev.1.10 page 101 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics table 5.18 output values of voltage (1) conditions: 1.8 v vcc = vcc_usb = avcc0 < 2.7 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output ports normal output mode v ol ?0.8vi ol = 0.5 ma high-drive output mode ? 0.8 i ol = 1.0 ma output high all output ports normal output mode ports 03, 05, 07, ports 40 to 47 v oh avcc0 ? 0.5 ? v i oh = ?0.5 ma ports other than above vcc ? 0.5 ? high-drive output mode vcc ? 0.5 ? i oh = ?1.0 ma table 5.19 output values of voltage (2) conditions: 2.7 v vcc = vcc_usb = avcc0 < 4.0 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output ports (except for riic) normal output mode v ol ?0.8vi ol = 1.0 ma high-drive output mode ? 0.8 i ol = 2.0 ma riic pins standard mode (normal output mode) ?0.4 i ol = 3.0 ma fast mode (high-drive output mode) ?0.6 i ol = 6.0 ma output high all output ports normal output mode ports 03, 05, 07, ports 40 to 47 v oh avcc0 ? 0.8 ? v i oh = ?1.0 ma ports other than above vcc ? 0.8 high-drive output mode vcc ? 0.8 ? i oh = ?2.0 ma table 5.20 output values of voltage (3) conditions: 4.0 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output ports (except for riic) normal output mode v ol ?0.8vi ol = 2.0 ma high-drive output mode ? 0.8 i ol = 4.0 ma riic pins standard mode(normal output mode) ?0.4 i ol = 3.0 ma fast mode (high-drive output mode) ?0.6 i ol = 6.0 ma output high all output ports normal output mode ports 03, 05, 07, ports 40 to 47 v oh avcc0 ? 0.8 ? v i oh = ?2.0 ma ports other than above vcc ? 0.8 ? high-drive output mode vcc ? 0.8 ? i oh = ?4.0 ma
r01ds0261ej0110 rev.1.10 page 102 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.2.1 normal i/o pin out put characteristics (1) figure 5.8 to figure 5.12 show the characteristics when normal output is se lected by the drive cap acity control register. figure 5.8 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when normal output is selected (reference data) figure 5.9 v oh /v ol and i oh /i ol temperature characteristics at vcc = 1.8 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol i oh /i ol [ma] vcc = 5.5v vcc = 3.3v vcc = 2.7v vcc = 1.8v vcc = 1.8v vcc = 2.7v vcc = 3.3v 0123456 vcc = 5.5v 50 40 30 20 10 0 -10 -20 -30 -40 -50 -60 v oh /v ol [v] v oh /v ol [v] 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 i oh /i ol [ma] 0 2 4 6 8 -2 -4 -6 -8 ta = 105c ta = 25c ta = -40c ta = 105c ta = 25c ta = -40c i oh /i ol vs v oh /v ol
r01ds0261ej0110 rev.1.10 page 103 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.10 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when normal output is selected (reference data) figure 5.11 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when normal output is selected (reference data) v oh /v ol [v] 00 . 5 1 . 5 1 2.5 3 i oh /i ol [ma] 0 5 10 15 20 -5 -10 -15 -20 ta = 105c ta = 25c ta = -40c ta = 105c ta = 25c ta = -40c i oh /i ol vs v oh /v ol 2 v oh /v ol [v] 00 . 5 1 . 5 1 2.5 3 i oh /i ol [ma] 0 10 20 -10 -20 ta = 105c ta = 25c ta = -40c ta = 105c ta = 25c ta = -40c i oh /i ol vs v oh /v ol 2 3.5 30 -30
r01ds0261ej0110 rev.1.10 page 104 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.12 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when normal output is selected (reference data) v oh /v ol [v] 00 . 5 1 . 5 1 2.5 3 i oh /i ol [ma] 0 10 20 -10 -20 ta = 105c ta = 25c ta = -40c ta = 105c ta = 25c ta = -40c i oh /i ol vs v oh /v ol 2 3.5 30 -30
r01ds0261ej0110 rev.1.10 page 105 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.2.2 normal i/o pin out put characteristics (2) figure 5.13 to figure 5.17 show the characteristics when high-drive output is select ed by the drive capacity control register. figure 5.13 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when high-drive output is selected (reference data) figure 5.14 v oh /v ol and i oh /i ol temperature characteristics at vcc = 1.8 v when high-drive output is selected (reference data) 0123456 -150 -100 -50 0 50 100 150 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] vcc=3.3v vcc=3.3v vcc=2.7v vcc=2.7v vcc=1.8v vcc=1.8v vcc=5.5v vcc=5.5v v oh /v ol [v] 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 i oh /i ol [ma] 0 4 8 12 16 -4 -8 -12 -16 ta = 105c ta = 25c ta = -40c ta = 105c ta = 25c ta = -40c i oh /i ol vs v oh /v ol
r01ds0261ej0110 rev.1.10 page 106 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.15 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when high-drive output is selected (reference data) figure 5.16 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when high-drive output is selected (reference data) v oh /v ol [v] 00 . 5 11 . 5 2 2.5 3 i oh /i ol [ma] 0 10 20 30 40 -20 -30 -40 -50 ta = 105c ta = 25c ta = -40c ta = 105c ta = 25c ta = -40c i oh /i ol vs v oh /v ol -10 50 v oh /v ol [v] 00 . 5 11 . 5 2 2.5 3 i oh /i ol [ma] 0 20 40 -20 -40 -60 ta = 105c ta = 25c ta = -40c ta = 105c ta = 25c ta = -40c i oh /i ol vs v oh /v ol 60 3.5
r01ds0261ej0110 rev.1.10 page 107 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.17 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when high-drive output is selected (reference data) v oh /v ol [v] 0 4 1 5 23 i oh /i ol [ma] 0 50 100 -50 -150 ta = 105c ta = 25c ta = -40c ta = 105c ta = 25c ta = -40c i oh /i ol vs v oh /v ol 150 6 -100
r01ds0261ej0110 rev.1.10 page 108 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.2.3 normal i/o pin out put characteristics (3) figure 5.18 to figure 5.21 show the characteristics of the riic output pin. figure 5.18 v ol and i ol voltage characteristics of riic output pin at t a = 25c (reference data) figure 5.19 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 2.7 v (reference data) 0123456 0 20 40 60 80 100 120 i ol vs v ol v ol [v] i ol [ma] vcc=3.3v vcc=2.7v vcc=5.5v i ol [ma] ta = 25c ta = 105c ta = -40c i ol vs v ol 0 5 10 15 20 25 30 35 40 v ol [v] 00 . 511 . 52 2.5 3
r01ds0261ej0110 rev.1.10 page 109 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.20 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 3.3 v (reference data) figure 5.21 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 5.5 v (reference data) i ol vs v ol i ol [ma] v ol [v] 10 20 30 50 40 0 00.511.522.533.5 ta = 25c ta = 105c ta = -40c 60 ta = 105c i ol [ma] 20 40 80 60 0 0123456 100 120 140 i ol vs v ol v ol [v] ta = -40c ta = 25c
r01ds0261ej0110 rev.1.10 page 110 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.3 ac characteristics 5.3.1 clock timing note 1. the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when fclk is in use at bel ow 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk must be within 3.5%. note 3. the vcc_usb range is 3.0 to 5.5 v when the usb clock is in use. note 4. the maximum operating frequency listed abov e does not include errors of the external oscillator and internal oscillator. for details on the range for the guaranteed oper ation, see table 5.26, clock timing. note 1. the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk must be within 3.5%. note 3. the vcc_usb range is 3.0 to 5.5 v when the usb clock is in use. note 4. the maximum operating frequency listed abov e does not include errors of the external oscillator and internal oscillator. for details on the range for the guaranteed oper ation, see table 5.26, clock timing. table 5.21 operating frequency value (high-speed operating mode) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol vcc unit 1.8 v vcc < 2.4 v 2.4 v vcc < 2.7 v 2.7 v vcc 5.5 v when usb is in use* 3 maximum operating frequency* 4 system clock (iclk) f max 81 65 45 4m h z flashif clock (fclk)* 1, * 2 81 63 23 2 peripheral module clock (pclka) 8 16 54 54 peripheral module clock (pclkb) 8 16 32 32 peripheral module clock (pclkd) 8 32 54 54 external bus clock (bclk) 8 16 32 32 bclk pin output 8 8 16 16 usb clock (uclk) f usb ???4 8 table 5.22 operating frequency value (middle-speed operating mode) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol vcc unit 1.8 v vcc < 2.4 v 2.4 v vcc < 2.7 v 2.7 v vcc 5.5 v when usb is in use* 3 maximum operating frequency* 4 system clock (iclk) f max 81 21 21 2m h z flashif clock (fclk)* 1, * 2 81 21 21 2 peripheral module clock (pclka) 8 12 12 12 peripheral module clock (pclkb) 8 12 12 12 peripheral module clock (pclkd) 8 12 12 12 external bus clock (bclk) 8 12 12 12 bclk pin output 8 8 12 12 usb clock (uclk) f usb ???4 8
r01ds0261ej0110 rev.1.10 page 111 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. programming and erasing t he flash memory is impossible. note 2. the a/d converter cannot be used. note 3. the maximum operating frequency list ed above does not include errors of the exte rnal oscillator. for details on the rang e for the guaranteed operation, see table 5.26, clock timing. table 5.23 operating frequency value (low-speed operating mode) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol vcc unit 1.8 v vcc < 2.4 v 2.4 v vcc < 2.7 v 2.7 v vcc 5.5 v maximum operating frequency* 3 system clock (iclk) f max 32.768 khz flashif clock (fclk)* 1 32.768 peripheral module clock (pclka) 32.768 peripheral module clock (pclkb) 32.768 peripheral module clock (pclkd)* 2 32.768 external bus clock (bclk) 32.768 bclk pin output 32.768 table 5.24 bclk clock timing (1) conditions: 2.7 v vcc= vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, fbclk 32 mhz (bclk pin output frequency 16 mhz), t a = ?40 to +105c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 62.5 ? ? ns figure 5.22 bclk pin output high pulse width t ch 15 ? ? ns bclk pin output low pulse width t cl 15 ? ? ns bclk pin output rise time t cr ??12ns bclk pin output fall time t cf ??12ns table 5.25 bclk clock timing (2) conditions: 1.8 v vcc = vcc_usb = avcc0 < 2.7 v, vss = avss0 = vrefl0 = vss_usb = 0 v, fbclk 16 mhz (bclk pin output frequency 8 mhz), t a = ?40 to +105c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 125 ? ? ns figure 5.22 bclk pin output high pulse width t ch 30 ? ? ns bclk pin output low pulse width t cl 30 ? ? ns bclk pin output rise time t cr ??25ns bclk pin output fall time t cf ??25ns
r01ds0261ej0110 rev.1.10 page 112 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. time until the clock can be used af ter the main clock oscillator stop bit (m osccr.mostp) is set to 0 (operating). note 2. reference values when an 8-mhz resonator is used. when specifying the main clock oscillator st abilization time, set the moscwtcr register with a stabilization time value that is equal to or greater than the resonator-manufacturer-recommended value. after the mosccr.mostp bit is changed to enable the main cloc k oscillator, confirm that the oscovfsr.moovf flag has become 1, and then start using the main clock. note 3. the vcc range should be 2.4 to 5.5 v when the pll is used. note 4. reference values when a 32.768-khz resonator is used. after the setting of the sosccr.sostp bit or rcr3.rtcen bit is changed to operate the sub-clock oscillator, only start using the sub-clock after the sub-clock oscillation stabilizati on wait time that is equal to or greater than the oscillator-manufactu rer- recommended value has elapsed. note 5. the vcc range should be 3.0 to 5.5 v when the usbpll is used. note 6. the input frequency can be set to 6 or 8 mhz and the oscillation frequency can be set to 48 mhz only. note 7. only 32.768 khz can be used. table 5.26 clock timing conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions extal external clock input cycle time t xcyc 50 ? ? ns figure 5.23 extal external clock input high pulse width t xh 20 ? ? ns extal external clock input low pulse width t xl 20 ? ? ns extal external clock rise time t xr ?? 5 ns extal external clock fall time t xf ?? 5 ns extal external clock input wait time * 1 t xwt 0.5 ? ? s main clock oscill ator oscillation frequency * 2 2.4 vcc 5.5 f main 1?20mhz 1.8 vcc < 2.4 1 ? 8 main clock oscillation st abilization time (crystal) * 2 t mainosc ? 3 ? ms figure 5.24 main clock oscillation stabilization time (ceramic resonator) * 2 t mainosc ?50? s loco clock oscillation frequency f loco 3.44 4.0 4.56 mhz loco clock oscillati on stabilization time t loco ??0.5 s figure 5.25 iwdt-dedicated clock oscillation frequency f iloco 12.75 15 17.25 khz iwdt-dedicated clock oscillati on stabilization time t iloco ??50 s figure 5.26 hoco clock oscillation frequency f hoco (32 mhz) 31.52 32 32.48 mhz t a = ?40 to + 85c 31.68 32 32.32 t a = 0 to + 55c 31.36 32 32.64 t a = ?40 to +105c f hoco (54 mhz) 53.19 54 54.81 mhz t a = ?40 to + 85c 53.46 54 54.54 t a = 0 to + 55c 52.92 54 55.08 t a = ?40 to +105c hoco clock oscillati on stabilization time t hoco ??30 s figure 5.28 pll input frequency * 3 f pllin 4 ? 12.5 mhz pll circuit oscillation frequency * 3 f pll 24 ? 54 mhz pll clock oscillation stabilization time t pll ??50 s figure 5.29 pll free-running oscillation frequency f pllfr ?8?mhz usbpll input frequency * 5 f pllin ?6, 8* 6 ?mhz usbpll circuit oscillation frequency * 5 f pll ? 48* 6 ?mhz usbpll clock oscillati on stabilization time t pll ??50 s figure 5.29 sub-clock oscillator oscillation frequency * 7 f sub ? 32.768 ? khz sub-clock oscillation stabilization time * 4 t subosc ? 0.5 ? s figure 5.30
r01ds0261ej0110 rev.1.10 page 113 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.22 bclk pin output timing figure 5.23 extal external clock input timing figure 5.24 main clock oscillation start timing figure 5.25 loco clock oscillation start timing t cf t ch t bcyc t cr t cl bclk pin output test conditions: v oh = vcc 0.7, v ol = vcc 0.3, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf t xh t xcyc extal external clock input vcc 0.5 t xl t xr t xf main clock oscillator output mosccr.mostp t mainosc loco clock oscillator output lococr.lcstp t loco
r01ds0261ej0110 rev.1.10 page 114 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.26 iwdt-dedicated cl ock oscillation start timing figure 5.27 hoco clock osci llation start timing (after reset is canceled by setting ofs1.hocoen bit to 0) figure 5.28 hoco clock os cillation start timing (oscillation is started by setting hococr.hcstp bit) figure 5.29 pll clock oscillation start timing (pll is operated after main cl ock oscillation has been stabled) iwdt-dedicated cloc k oscillator output ilococr.ilcstp t iloco res# internal reset hoco clock ofs1.hocoen t reswt hoco clock hococr.hcstp t hoco pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillator output t pll
r01ds0261ej0110 rev.1.10 page 115 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.30 sub-clock oscillation start timing sub-clock oscillator output sosccr.sostp t subosc
r01ds0261ej0110 rev.1.10 page 116 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.3.2 reset timing note 1. when ofs1.(lvdas, faststup) bits are 11b. note 2. when ofs1.(lvdas, faststup) bits are a value other than 11b. note 3. when iwdtcr.cks[3:0] bits are 0000b. note 4. when wdtcr.cks[3:0] bits are 0001b. figure 5.31 reset input timing at power-on figure 5.32 reset input timing (1) figure 5.33 reset input timing (2) table 5.27 reset timing conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions res# pulse width at power-on t reswp 3 ? ? ms figure 5.31 other than above t resw 30 ? ? s figure 5.32 wait time after res# cancellation (at power-on) at normal startup* 1 t reswt ? 8.5 ? ms figure 5.31 during fast startup time* 2 t reswt ? 560 ? s wait time after res# cancellation (during powered-on state) t reswt ? 120 ? s figure 5.32 independent watchdog timer reset period t reswiw ? 1 ? iwdt clock cycle figure 5.33 watchdog timer reset period t reswww ? 4 ? pclkb cycle software reset period t reswsw ? 1 ? iclk cycle wait time after independent watchdog timer reset cancellation* 3 t reswt2 ? 300 ? s wait time after watchdog timer reset cancellation* 4 t reswt2 ? 300 ? s wait time after software reset cancellation t reswt2 ? 170 ? s vcc res# t reswp internal reset t reswt res# internal reset t reswt t resw independent watchdog timer reset watchdog timer reset software reset internal reset t reswt2 t reswiw , t reswww , t reswsw
r01ds0261ej0110 rev.1.10 page 117 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes note 1. the recovery time varies depending on the state of each os cillator when the wait instruction is executed. when multiple oscillators are operating, the recovery time varies depending on t he operating state of the oscillators that are not selected a s the system clock source. the above table applies when only the corresponding clock is operating. note 2. when the frequency of the crystal is 20 mhz. when the main clock oscillator wait contro l register (moscwtcr) is set to 04h. note 3. when the frequency of the external clock is 20 mhz. when the main clock oscillator wait contro l register (moscwtcr) is set to 00h. note 1. the recovery time varies depending on the state of each os cillator when the wait instruction is executed. when multiple oscillators are operating, the recovery time varies depending on t he operating state of the oscillators that are not selected a s the system clock source. the above table applies when only the corresponding clock is operating. note 2. when the frequency of the crystal is 12 mhz. when the main clock oscillator wait contro l register (moscwtcr) is set to 04h. note 3. when the frequency of pll is 12 mhz. when the main clock oscillator wait contro l register (moscwtcr) is set to 04h. note 4. when the frequency of the external clock is 12 mhz. when the main clock oscillator wait contro l register (moscwtcr) is set to 00h. note 5. when the frequency of pll is 12 mhz. when the main clock oscillator wait contro l register (moscwtcr) is set to 00h. note 6. this is the case when hoco is selected as the system clock and its frequency division is set to be 8 mhz. table 5.28 timing of recovery from low power consumption modes (1) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 high-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc ? 2 3 ms figure 5.34 external clock input to main clock oscillator main clock oscillator operating* 3 t sbyex ?3550 s sub-clock oscillator operating t sbysc ? 650 800 s hoco clock oscillator operating t sbyho ?4055 s loco clock oscillator operating t sbylo ?4055 s table 5.29 timing of recovery from low power consumption modes (2) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 middle-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc ? 2 3 ms figure 5.34 main clock oscillator and pll circuit operating* 3 t sbypc ?2 3ms external clock input to main clock oscillator main clock oscillator operating* 4 t sbyex ?3 4 s main clock oscillator and pll circuit operating* 5 t sbype ?6585 s sub-clock oscillator operating t sbysc ? 600 750 s hoco clock oscillator operating* 6 t sbyho ?4050 s loco clock oscillator operating t sbylo ?5 7 s
r01ds0261ej0110 rev.1.10 page 118 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. the sub-clock conti nues oscillating in software standby mode during low-speed mode. figure 5.34 software standby mode recovery timing note 1. oscillators continue oscillating in deep sleep mode. note 2. when the frequency of the system clock is 32 mhz. note 3. when the frequency of the system clock is 12 mhz. note 4. when the frequency of the system clock is 32 khz. table 5.30 timing of recovery from low power consumption modes (3) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 low-speed mode sub-clock oscillator operating t sbysc ? 600 750 s figure 5.34 table 5.31 timing of recovery from low power consumption modes (4) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from deep sleep mode* 1 high-speed mode* 2 t dslp ?23.5 s figure 5.35 middle-speed mode* 3 t dslp ?3 4 s low-speed mode* 4 t dslp ? 400 500 s oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbysc, t sbyho, t sbylo
r01ds0261ej0110 rev.1.10 page 119 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.35 deep sleep mode recovery timing note: values when the frequencies of pclka, pclkb, pclkd, fclk, and bclk are not divided. table 5.32 operating mode transition time conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c mode before transition mode after transition iclk frequency transition time unit min. typ. max. high-speed operating mode middle-speed operating modes 8 mhz ? 10 ? s middle-speed operating modes high-speed operating mode 8 mhz ? 37.5 ? s low-speed operating mode middle-speed operating mode, high-speed operating mode 32.768 khz ? 215 ? s middle-speed operating mode, high-speed operating mode low-speed operating mode 32.768 khz ? 185 ? s oscillator iclk irq deep sleep mode t dslp
r01ds0261ej0110 rev.1.10 page 120 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.3.4 control signal timing note: 200 ns minimum in software standby mode. note 1. t pcyc indicates the cycle of pclkb. note 2. t nmick indicates the cycle of the nmi digital filter sampling clock. note 3. t irqck indicates the cycle of th e irqi digital filter samp ling clock (i = 0 to 7). figure 5.36 nmi interrupt input timing figure 5.37 irq interrupt input timing table 5.33 control signal timing conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ? ? ns nmi digital filter is disabled (nmiflte.nflten = 0) t pcyc 2 200 ns t pcyc 2* 1 ?? t pcyc 2 > 200 ns 200 ? ? nmi digital filter is enabled (nmiflte.nflten = 1) t nmick 3 200 ns t nmick 3.5* 2 ?? t nmick 3 > 200 ns irq pulse width t irqw 200 ? ? ns irq digital filter is disabled (irqflte0.flteni = 0) t pcyc 2 200 ns t pcyc 2* 1 ?? t pcyc 2 > 200 ns 200 ? ? irq digital filter is enabled (irqflte0.flteni = 1) t irqck 3 200 ns t irqck 3.5* 3 ?? t irqck 3 > 200 ns nmi t nmiw irq t irqw
r01ds0261ej0110 rev.1.10 page 121 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.3.5 bus timing table 5.34 bus timing (1) conditions: 2.7 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, fbclk 32 mhz (bclk pin output frequency 16 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c l = 30 pf, when normal output is selected by the drive capac ity control register item symbol min. max. unit test conditions address delay time t ad ? 55 ns figure 5.38 to figure 5.41 byte control delay time t bcd ?5 5n s cs# delay time t csd ?5 5n s rd# delay time t rsd ?5 5n s read data setup time t rds 40 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?5 5n s write data delay time t wdd ?5 5n s write data hold time t wdh 0?n s wait# setup time t wts 40 ? ns figure 5.42 wait# hold time t wth 0?n s table 5.35 bus timing (2) conditions: 1.8 v vcc = vcc_usb = avcc0 < 2.7 v, vss = avss0 = vss_usb = 0 v, fbclk 16 mhz (bclk pin output frequency 8 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c l = 30 pf, when normal output is selected by the drive capac ity control register item symbol min. max. unit test conditions address delay time t ad ? 90 ns figure 5.38 to figure 5.41 byte control delay time t bcd ?9 0n s cs# delay time t csd ?9 0n s rd# delay time t rsd ?9 0n s read data setup time t rds 60 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?9 0n s write data delay time t wdd ?9 0n s write data hold time t wdh 0?n s wait# setup time t wts 60 ? ns figure 5.42 wait# hold time t wth 0?n s
r01ds0261ej0110 rev.1.10 page 122 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.38 external bus timing/normal read cycle (bus clock synchronization) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 d15 to d0 (read) byte-write strobe mode 1-write strobe mode bc1#, bc0# common to byte-write strobe mode and 1-write strobe mode t bcd t csd rd# (read) t rsd t rsd t ad t rdh t rds t ad t ad t w1 t w2 t end t n1 t n2 rdon:1 csrwait:2 csroff:2 cson:0 t bcd t csd
r01ds0261ej0110 rev.1.10 page 123 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.39 external bus timing/normal write cycle (bus clock synchronization) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 byte-write strobe mode 1-write strobe mode bc1#, bc0# common to byte-write strobe mode and 1-write strobe mode t bcd t csd t ad t ad t ad d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w1 t w2 t end t n1 t n2 wron:1 wdon:1 *1 cswwait:2 wdoff:1 *1 cson:0 t bcd t csd cswoff:2 note 1. be sure to specify wdon and wdoff as at least one cycle of bclk.
r01ds0261ej0110 rev.1.10 page 124 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.40 external bus timing/page read cycle (bus clock synchronization) figure 5.41 external bus timing/page wr ite cycle (bus clock synchronization) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 d15 to d0 (read) byte-write strobe mode 1-write strobe mode bc1#, bc0# common to byte-write strobe mode and 1-write strobe mode t bcd t csd rd# (read) t rsd t rsd t rdh t rds t ad t w1 t w2 t end t pw1 t pw2 t ad t ad t rsd t rsd t rdh t rds t rsd t rsd t rdh t rds t end t pw1 t pw2 t end t n1 t h t ad t ad t ad t ad rdon:1 csrwait:2 csroff:1 t rsd t rsd t rdh t rds t ad t ad csprwait:2 t pw1 t pw2 t end rdon:1 csprwait:2 rdon:1 csprwait:2 rdon:1 cson:0 t bcd t csd a23 to a1 cs3# to cs0# t ad bclk a23 to a0 byte-write strobe mode 1-write strobe mode bc1#, bc0# common to byte-write strobe mode and 1-write strobe mode t bcd t csd t ad t w1 d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w2 t end t pw1 t pw2 t ad t ad t wrd t wrd t wdh t wdd t wrd t wrd t wdh t wdd t dw1 t end t pw1 t pw2 t end t n1 t h t dw1 t ad t ad t ad t ad wron:1 wdon:1 *1 cswwait:2 cspwwait:2 wdoff:1 *1 cspwwait:2 wdoff:1 *1 cswoff:1 wdoff:1 *1 cson:0 wron:1 wdon:1 *1 wron:1 wdon:1 *1 t bcd t csd note 1. be sure to specify wdon and wdoff as at least one cycle of bclk.
r01ds0261ej0110 rev.1.10 page 125 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.42 external bus timing/external wait control t wts t wth t wts t wth csrwait:3 cswwait:3 bclk a23 to a0 cs3# to cs0# rd# (read) wr# (write) wait# t w1 t w2 (t end )t end t w3 t n1 t h external wait
r01ds0261ej0110 rev.1.10 page 126 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics table 5.36 bus timing (multiplex bus) (1) conditions: 2.7 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, fbclk 32 mhz (bclk pin output frequency 16 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c l = 30 pf, when normal output is selected by the drive capac ity control register item symbol min. max. unit test conditions address delay time t ad ? 55 ns figure 5.43, figure 5.44 byte control delay time t bcd ?5 5n s cs# delay time t csd ?5 5n s rd# delay time t rsd ?5 5n s ale delay time t aled ?5 5n s read data setup time t rds 40 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?5 5n s write data delay time t wdd ?5 5n s write data hold time t wdh 0?n s wait# setup time t wts 40 ? ns figure 5.42 wait# hold time t wth 0?n s table 5.37 bus timing (multiplex bus) (2) conditions: 1.8 v vcc = vcc_usb = avcc0 < 5.5 v, vss = avss0 = vss_usb = 0 v, fbclk 16 mhz (bclk pin output frequency 8 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c l = 30 pf, when normal output is selected by the drive capac ity control register item symbol min. max. unit test conditions address delay time t ad ? 90 ns figure 5.43, figure 5.44 byte control delay time t bcd ?9 0n s cs# delay time t csd ?9 0n s rd# delay time t rsd ?9 0n s ale delay time t aled ?9 0n s read data setup time t rds 60 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?9 0n s write data delay time t wdd ?9 0n s write data hold time t wdh 0?n s wait# setup time t wts 60 ? ns figure 5.42 wait# hold time t wth 0?n s
r01ds0261ej0110 rev.1.10 page 127 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.43 external bus timing/read access operation example (multiplex) figure 5.44 external bus timing/write access operat ion example (multiplex) address/ data bus data read (rd#) t ad bclk address address latch (ale) chip select (cs3# to cs0#) t w1 t wn t ad t ad t su(db-rd) 40ns(min) t end address cycle data cycle t aled t csd t csd t n1 t h fixed to 1 cycle wait for address cycle (await) t rsd t rss t rsd t rss cs extended cycle when reading (csroff) t aled wait for rd assertion (rdon) wait for normal read cycle (csrwait) wait for cs assertion (cson) a d t rdh t rds t d(ad-ale) t h(ale-ad) t h(rd-db) 0ns(min) address/ data bus data write (wr#) t ad bclk address address latch (ale) chip select (cs3# to cs0#) t w1 t ad t ad t end address cycle data cycle t csd t csd t n1 t h fixed to 1 cycle t d(bclk-ale)= t aled wait for address cycle (await) t rsd t rss t rsd t rss wait for wr assertion (wron) wait for normal write cycle (cswwait) a d wait for write data output (wdon) t h(bclk-ale)= t aled a cs extended cycle when writing (cswoff)
r01ds0261ej0110 rev.1.10 page 128 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.3.6 timing of on-chi p peripheral modules note 1. t pcyc : pclk cycle note 2. t cac : cac count clock source cycle note 3. when the loco is selected as the clock output source (the ckocr.ckosel[2:0] bits are 000b), set the clock output divisio n ratio selection to divided by 2 (the ckocr.ckodiv[2:0] bits are 001b). note 4. when the extal external clock input or an oscillator is used with divided by 1 (the ckocr.ckosel[2:0] bits are 010b and the ckocr.ckodiv[2:0] bits are 000b) to output from clkout, the above should be satisfied with an input duty cycle of 45 to 55%. table 5.38 timing of on-chip peripheral modules (1) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit *1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.45 mtu2/tpu input capture input pulse width single-edge setting t ticw 1.5 ? t pcyc figure 5.46 both-edge setting 2.5 ? timer clock pulse width single-edge setting t tckwh, t tckwl 1.5 ? t pcyc figure 5.47 both-edge setting 2.5 ? phase counting mode 2.5 ? poe2 poe# input pulse width t poew 1.5 ? t pcyc figure 5.48 tmr timer clock pulse width single-edge setting t tmcwh , t tmcwl 1.5 ? t pcyc figure 5.49 both-edge setting 2.5 ? sci input clock cycle time asynchronous t scyc 4?t pcyc figure 5.50 clock synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?20ns input clock fall time t sckf ?20ns output clock cycle time asynchronous t scyc 16 ? t pcyc figure 5.51 clock synchronous 4 ? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?20ns output clock fall time t sckf ?20ns transmit data delay time (master) clock synchronous t txd ?40ns transmit data delay time (slave) clock synchronous 2.7 v or above ? 65 ns 1.8 v or above ? 100 ns receive data setup time (master) clock synchronous 2.7 v or above t rxs 65 ? ns 1.8 v or above 90 ? ns receive data setup time (slave) clock synchronous 40 ? ns receive data hold time clock synchronous t rxh 40 ? ns a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.52 cac cacref input pulse width t pcyc t cac *2 t cacref 4.5 t cac + 3 t pcyc ?ns t pcyc > t cac *2 5 t cac + 6.5 t pcyc clkout clkout pin output cycle *4 vcc = 2.7 v or above t ccyc 62.5 ? ns figure 5.53 vcc = 1.8 v or above 125 clkout pin high pulse width *3 vcc = 2.7 v or above t ch 15 ? ns vcc = 1.8 v or above 30 clkout pin low pulse width *3 vcc = 2.7 v or above t cl 15 ? ns vcc = 1.8 v or above 30 clkout pin output rise time vcc = 2.7 v or above t cr ?12ns vcc = 1.8 v or above 25 clkout pin output fall time vcc = 2.7 v or above t cf ?12ns vcc = 1.8 v or above 25
r01ds0261ej0110 rev.1.10 page 129 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. t pcyc : pclk cycle note 2. n: an integer from 1 to 8 that can be set by the rspi clock delay register (spckd) note 3. n: an integer from 1 to 8 that can be set by the rspi slave select negation delay register (sslnd) table 5.39 timing of on-chip peripheral modules (2) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c, c = 30 pf, when high-drive output is selected by the drive capacity control register item symbol min. max. unit test conditions rspi rspck clock cycle master t spcyc 2 4096 t pcyc * 1 figure 5.54 slave 8 4096 rspck clock high pulse width master t spckwh (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock low pulse width master t spckwl (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock rise/fall time output 2.7 v or above t spckr, t spckf ?1 0n s 1.8 v or above ? 15 input ? 1 s data input setup time master 2.7 v or above t su 10 ? ns figure 5.55 to figure 5.58 1.8 v or above 30 ? slave 25 ? t pcyc ? data input hold time master rspck set to a division ratio other than pclkb divided by 2 t h t pcyc ?ns rspck set to pclkb divided by 2 t hf 0? slave t h 20 + 2 t pcyc ? ssl setup time master t lead ?30 + n* 2 t spcyc ?ns slave 2 ? t pcyc ssl hold time master t lag ?30 + n* 3 t spcyc ?ns slave 2 ? t pcyc data output delay time master 2.7 v or above t od ?1 4n s 1.8 v or above ? 30 slave 2.7 v or above ? 3 t pcyc + 65 1.8 v or above ? 3 t pcyc +105 data output hold time master t oh 0?n s slave 0 ? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi and miso rise/fall time output 2.7 v or above t dr, t df ?1 0n s 1.8 v or above ? 15 input ? 1 s ssl rise/fall time output 2.7 v or above t sslr, t sslf ?1 0n s 1.8 v or above ? 15 ns input ? 1 s slave access time 2.7 v or above t sa ?6t pcyc figure 5.57, figure 5.58 1.8 v or above ? 7 slave output release time 2.7 v or above t rel ?5t pcyc 1.8 v or above ? 6
r01ds0261ej0110 rev.1.10 page 130 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note 1. t pcyc : pclk cycle table 5.40 timing of on-chip peripheral modules (3) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc figure 5.54 sck clock cycle input (slave) 6 65536 t pcyc sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?20ns data input setup time (master) 2.7 v or above t su 65 ? ns figure 5.55, figure 5.56 1.8 v or above 95 ? data input setup time (slave) 40 ? data input hold time t h 40 ? ns ssl input setup time t lead 3?t spcyc ssl input hold time t lag 3?t spcyc data output delay time (master) t od ?40ns data output delay time (slave) 2.7 v or above ? 65 1.8 v or above ? 100 data output hold time (master) 2.7 v or above t oh ?10 ? ns 1.8 v or above ?20 ? data output hold time (slave) ?10 ? data rise/fall time t dr , t df ?20ns ssl input rise/fall time t sslr , t sslf ?20ns slave access time t sa ?6t pcyc figure 5.57, figure 5.58 slave output release time t rel ?6t pcyc
r01ds0261ej0110 rev.1.10 page 131 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: t iiccyc : riic internal reference clock (iic ) cycle note 1. the value in parentheses is used when the icmr3.nf[1:0] bits are set to 11b while a digital filter is enabled with the i cfer.nfe bit = 1. note 2. c b is the total capacitance of the bus lines. table 5.41 timing of on-chip peripheral modules (4) conditions: 2.7 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, fpclkb 32 mhz, t a = ?40 to +105c item symbol min.* 1, * 2 max. unit test conditions riic (standard mode, smbus) scl cycle time t scl 6 (12) t iiccyc + 1300 ? ns figure 5.59 scl high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda rise time t sr ? 1000 ns scl, sda fall time t sf ? 300 ns scl, sda spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition hold time t stah t iiccyc + 300 ? ns repeated start condition setup time t stas 1000 ? ns stop condition setup time t stos 1000 ? ns data setup time t sdas t iiccyc + 50 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast mode) scl cycle time t scl 6 (12) t iiccyc + 600 ? ns figure 5.59 scl high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda rise time t sr ? 300 ns scl, sda fall time t sf ? 300 ns scl, sda spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition hold time t stah t iiccyc + 300 ? ns repeated start condition setup time t stas 300 ? ns stop condition setup time t stos 300 ? ns data setup time t sdas t iiccyc + 50 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0261ej0110 rev.1.10 page 132 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: t pcyc : pclk cycle note 1. c b is the total capacitance of the bus lines. table 5.42 timing of on-chip peripheral modules (5) conditions: 2.7 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, fpclkb 32 mhz, t a = ?40 to +105c item symbol min.* 1 max. unit test conditions simple i 2 c (standard mode) sda rise time t sr ? 1000 ns figure 5.59 sda fall time t sf ? 300 ns sda spike pulse removal time t sp 04 t pcyc ns data setup time t sdas 250 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf simple i 2 c (fast mode) sda rise time t sr ? 300 ns figure 5.59 sda fall time t sf ? 300 ns sda spike pulse removal time t sp 04 t pcyc ns data setup time t sdas 100 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf table 5.43 timing of on-chip peripheral modules (6) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, fpclkb 32 mhz, t a = ?40 to +105c item symbol min. max. unit test conditions ssi audio_mclk input frequency 2.7 v or above t audio 12 5m h z 1.8 v or above 1 4 output clock cycle t o 250 ? ns figure 5.60 input clock cycle t i 250 ? ns clock high level t hc 0.4 0.6 to, ti clock low level t lc 0.4 0.6 to, ti clock rise time t rc ?2 0n s data delay time 2.7 v or above t dtr ? 65 ns figure 5.61 figure 5.62 1.8 v or above ? 105 setup time 2.7 v or above t sr 65 ? ns 1.8 v or above 90 ? hold time t htr 40 ? ns ws changing edge ssidata output delay t dtrw ? 105 ns figure 5.63
r01ds0261ej0110 rev.1.10 page 133 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.45 i/o port input timing figure 5.46 mtu2 input/output timing figure 5.47 mtu2 clock input timing figure 5.48 poe# input timing port pclk t prw output compare output input capture input pclk t ticw mtclka to mtclkd pclk t tckwl t tckwh poen# input pclk t poew
r01ds0261ej0110 rev.1.10 page 134 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.49 tmr clock input timing figure 5.50 sck clock input timing figure 5.51 sci input/output timing: clock synchronous mode pclk tmci0 to tmci3 t tmcwl t tmcwh t sckw t sckr t sckf t scyc sckn n = 0, 1, 5, 6, 8, 9, 12 t txd t rxs t rxh txdn rxdn sckn n = 0, 1, 5, 6, 8, 9, 12
r01ds0261ej0110 rev.1.10 page 135 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.52 a/d converter external trigger input timing figure 5.53 clkout output timing figure 5.54 rspi clock timing and simple spi clock timing adtrg0# pclk t trgw t cf t ch t ccyc t cr t cl clkout pin output test conditions: v oh = vcc 0.7, v ol = vcc 0.3, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc n = 0, 1, 5, 6, 8, 9, 12 sckn master select output sckn slave select input rspcka master select output rspcka slave select input simple spi rspi
r01ds0261ej0110 rev.1.10 page 136 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.55 rspi timing (master, cpha = 0) and simple spi clock timing (master, ckph = 1) figure 5.56 rspi timing (master, cpha = 1) and simple spi clock timing (master, ckph = 0) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output n = 0, 1, 5, 6, 8, 9, 12 simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi simple spi sckn ckpol = 1 output sckn ckpol = 0 output smison input smosin output t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od n = 0, 1, 5, 6, 8, 9, 12
r01ds0261ej0110 rev.1.10 page 137 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.57 rspi timing (sl ave, cpha = 0) and simple spi clock timing (slave, ckph = 1) figure 5.58 rspi timing (sl ave, cpha = 1) and simple spi clock timing (slave, ckph = 0) t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input n = 0, 1, 5, 6, 8, 9, 12 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sckn ckpol = 1 input sckn ckpol = 0 input smison output smosin input n = 0, 1, 5, 6, 8, 9, 12 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input
r01ds0261ej0110 rev.1.10 page 138 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.59 riic bus interface input/output timing and simple i 2 c bus interface input/output timing figure 5.60 ssi clock input/output timing figure 5.61 ssi transmission/re ception timing (ssicr.sckp=0) test conditions v ih = vcc 0.7, v il = vcc 0.3 sda scl v ih v il t stah t sclh t scll p *1 s *1 t sf t sr t scl t sdah t sdas t stas t sp t stos p *1 t buf sr *1 note 1. s, p, and sr indicate the following conditions, respectively. s: start condition p: stop condition sr: repeated start condition ssisckn t hc t lc t rc t i , t o t sr t htr t dtr ssisckn (input or output) ssiwsn, ssidatan, ssirxdn (input) ssiwsn, ssidatan, ssitxdn (output)
r01ds0261ej0110 rev.1.10 page 139 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.62 ssi transmission/re ception timing (ssicr.sckp=1) figure 5.63 ssidata ou tput delay after ssiwsn changing edge t sr t htr t dtr ssisckn (input or output) ssiwsn, ssidatan, ssirxdn (input) ssiwsn, ssidatan, ssitxdn (output) t dtrw ssiwsn (input) ssidatan (output) note. timing to output the msb bit during slave transmission from ssiwsn when del = 1 and sdta = 0 or del = 1, sdta = 1, and swl[2:0] = dwl[2:0]
r01ds0261ej0110 rev.1.10 page 140 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.4 usb characteristics figure 5.64 usb0_dp and usb0_dm output timing table 5.44 usb characteristics (usb0_d p and usb0_dm pin characteristics) conditions: 3.0 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions input characteristics input high level voltage v ih 2.0 ? v input low level voltage v il ?0 . 8v differential input sensitivity v di 0.2 ? v | usb0_dp ? usb0_dm | differential common mode range v cm 0.8 2.5 v output characteristics output high level voltage v oh 2.8 vcc_usb v i oh = ?200 a output low level voltage v ol 0.0 0.3 v i ol = 2 ma cross-over voltage v crs 1.3 2.0 v figure 5.64, figure 5.65 rise time fs t r 42 0n s ls 75 300 fall time fs t f 42 0n s ls 75 300 rise/fall time ratio fs t r /t f 90 111.11 % t r /t f ls 80 125 output resistance z drv 28 44 ? (adjusting the resistance by external elements is not necessary.) vbus characteristics vbus input voltage v ih vcc 0.8 ? v v il ?v c c 0 . 2v pull-up, pull-down pull-down resistor r pd 14.25 24.80 k ? pull-up resistor r pui 0.9 1.575 k ? during idle state r pua 1.425 3.09 k ? during reception battery charging specification ver 1.2 d+ sink current i dp_sink 25 175 a d- sink current i dm_sink 25 175 a dcd source current i dp_src 71 3 a data detection voltage v dat_ref 0.25 0.4 v d+ source current v dp_src 0.5 0.7 v output current = 250 a d- source current v dm_src 0.5 0.7 v output current = 250 a usb0_dp, usb0_dm t f t r 90% 10% 10% 90% v crs
r01ds0261ej0110 rev.1.10 page 141 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.65 test circuit observation point 50 pf 50 pf usb0_dp usb0_dm full-speed (fs) observation point 1.5 k ? 200 pf to 600 pf usb0_dp usb0_dm 200 pf to 600 pf 3.6 v observation point low-speed (ls)
r01ds0261ej0110 rev.1.10 page 142 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.5 a/d conversion characteristics figure 5.66 vrefh0 voltage range vs. avcc0 note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differe ntial non-linearity error, and inl integral non-linearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and th e comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.45 a/d conversion characteristics (1) conditions: 2.7 v vcc = vcc_usb = avcc0 5.5 v, 2.7 v vrefh0 avcc0, reference voltage = vrefh0 selected, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 54 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 54 mhz) permissible signal source impedance (max.) = 0.3 k ? 0.83 ? ? s high-precision channel the adcsr.adhsc bit is 0 the adsstrn register is 0dh 1.33 ? ? normal-precision channel the adcsr.adhsc bit is 0 the adsstrn register is 28h analog input capacitance cs ? ? 15 pf pin capacitance included figure 5.67 analog input resistance rs ? ? 2.5 k ? figure 5.67 analog input voltage range ain 0 ? vrefh0 v offset error ? 0.5 4.5 lsb high-precision channel 6.0 lsb other than above full-scale error ? 0.75 4.5 lsb high-precision channel 6.0 lsb other than above quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential non-linearity error ? 1.0 ? lsb inl integral non-linearity error ? 1.0 3.0 lsb vrefh0 5.0 4.0 3.0 2.0 1.0 1.0 2.0 3.0 4.0 5.0 a/d conversion characteristics (1) a/d conversion characteristics (2) adcsr.adhsc = 0 5.5 2.7 2.4 2.4 2.7 5.5 avcc0 vrefh0 5.0 4.0 3.0 2.0 1.0 1.0 2.0 3.0 4.0 5.0 a/d conversion characteristics (3) a/d conversion characteristics (4) adcsr.adhsc = 1 5.5 2.7 2.4 2.4 2.7 5.5 avcc0 a/d conversion characteristics (5) 1.8 1.8
r01ds0261ej0110 rev.1.10 page 143 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differe ntial non-linearity error, and inl integral non-linearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and th e comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.46 a/d conversion characteristics (2) conditions: 2.4 v vcc = vcc_usb = avcc0 5.5 v, 2.4 v vrefh0 avcc0, reference voltage = vrefh0 selected, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 32 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 32 mhz) permissible signal source impedance (max.) = 1.3 k ? 1.41 ? ? s high-precision channel the adcsr.adhsc bit is 0 the adsstrn register is 0dh 2.25 ? ? normal-precision channel the adcsr.adhsc bit is 0 the adsstrn register is 28h analog input capacitance cs ? ? 15 pf pin capacitance included figure 5.67 analog input resistance rs ? ? 2.5 k ? figure 5.67 offset error ? 0.5 4.5 lsb full-scale error ? 0.75 4.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential non-linearity error ? 1.0 ? lsb inl integral non-linearity error ? 1.0 4.5 lsb
r01ds0261ej0110 rev.1.10 page 144 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differe ntial non-linearity error, and inl integral non-linearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and th e comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.47 a/d conversion characteristics (3) conditions: 2.7v vcc = vcc_usb = avcc0 5.5v, 2.7v vrefh0 avcc0, reference voltage = vrefh0 selected, vss = avss0 = vrefl0 = vss_usb = 0v, ta = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 27 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 27 mhz) permissible signal source impedance (max.) = 1.1 k ? 2?? s high-precision channel the adcsr.adhsc bit is 1 the adsstrn.sst[7:0] bits are 0dh 3 ? ? normal-precision channel the adcsr.adhsc bit is 1 the adsstrn.sst[7:0] bits are 28h analog input capacitance cs ? ? 15 pf pin capacitance included figure 5.67 analog input resistance rs ? ? 2.5 k ? figure 5.67 offset error ? 0.5 4.5 lsb full-scale error ? 0.75 4.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential non-linearity error ? 1.0 ? lsb inl integral non-linearity error ? 1.0 3.0 lsb
r01ds0261ej0110 rev.1.10 page 145 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differe ntial non-linearity error, and inl integral non-linearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and th e comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.48 a/d conversion characteristics (4) conditions: 2.4v vcc = vcc_usb = avcc0 5.5v, 2.4v vrefh0 avcc0, vss = avss0 = vss_usb = 0v, reference voltage = vrefh0 selected, ta = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 16 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 16 mhz) permissible signal source impedance (max.) = 2.2 k ? 3.38 ? ? s high-precision channel the adcsr.adhsc bit is 1 the adsstrn register is 0dh 5.06 ? ? normal-precision channel the adcsr.adhsc bit is 1 the adsstrn register is 28h analog input capacitance cs ? ? 15 pf pin capacitance included figure 5.67 analog input resistance rs ? ? 2.5 k ? figure 5.67 offset error ? 0.5 4.5 lsb full-scale error ? 0.75 4.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential non-linearity error ? 1.0 ? lsb inl integral non-linearity error ? 1.0 3.0 lsb
r01ds0261ej0110 rev.1.10 page 146 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differe ntial non-linearity error, and inl integral non-linearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and th e comparison time. as the test conditions, the number of sampl ing states is indicated. figure 5.67 equivalent circuit table 5.49 a/d conversion characteristics (5) conditions: 1.8v vcc = vcc_usb = avcc0 5.5v, 1.8v vrefh0 avcc0, vss = avss0 = vss_usb = 0v, reference voltage = vrefh0 selected, ta = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 8 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 8 mhz) permissible signal source impedance (max.) = 5 k ? 6.75 ? ? s high-precision channel the adcsr.adhsc bit is 1 the adsstrn register is 0dh 10.13 ? ? normal-precision channel the adcsr.adhsc bit is 1 the adsstrn register is 28h analog input capacitance cs ? ? 15 pf pin capacitance included figure 5.67 analog input resistance rs ? ? 2.5 k ? figure 5.67 offset error ? 1 7.5 lsb full-scale error ? 1.5 7.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 3.0 8.0 lsb dnl differential non-linearity error ? 1.0 ? lsb inl integral non-linearity error ? 1.25 3.0 lsb table 5.50 a/d converter channel classification classification channel conditions remarks high-precision channel an000 to an007 avcc0 = 1.8 to 5.5 v pins an000 to an007 cannot be used as digital outputs when the a/d converter is in use. normal-precision channel an016 to an031 internal reference voltage input channel internal reference voltage avcc0 = 2.0 to 5.5 v temperature sensor input channel temperature sensor output avcc0 = 2.0 to 5.5 v 12b - adc cs rs r0 mcu
r01ds0261ej0110 rev.1.10 page 147 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.68 illustration of a/d converter characteristic terms absolute accuracy absolute accuracy is the difference betw een output code based on the theoretical a/d conversion char acteristics and the actual a/d conversion result. when measur ing absolute accuracy, the voltage at th e midpoint of the width of analog input voltage (1-lsb width), that can m eet the expectation of outp utting an equal code based on the theoretical a/d conversion characteristics, is us ed as an analog input voltage. for example, if 12-bit resolution is used and if reference voltage (vrefh0 = 3.072 v), then 1-lsb width becomes 0.75 mv, and 0 mv, 0.75 mv, 1.5 mv, ... are used as analog input voltages. if analog input voltage is 6 mv, absolute accuracy = 5 lsb means that the actual a/d conversion result is in the range of 003h to 00dh, although an output code, 008h, can be exp ected from the theoretical a/ d conversion characteristics. integral non-linearity error (inl) the integral non-linearity error is the maximum deviation betw een the ideal line when the m easured offset and full-scale errors are zeroed, and the actual output code. integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinear ity error (dnl) 1-lsb width for ideal a/d conversion characteristic vrefh0 (full-scale) a/d converter output code
r01ds0261ej0110 rev.1.10 page 148 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics differential non-lin earity error (dnl) the differential non-linearity error is the difference between 1-lsb width based on the ideal a/d conversion characteristics and the widt h of the actual output code. offset error an offset error is the difference between a transition point of the ideal first output code and the actual first output code. full-scale error a full-scale error is the difference between a transition point of the id eal last output code and the actual last output code.
r01ds0261ej0110 rev.1.10 page 149 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.6 d/a conversion characteristics table 5.51 d/a conversion characteristics (1) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c reference voltage = vrefh or vrefl selected item min. typ. max. unit test conditions resolution ? ? 12 bit resistive load 30 ? ? k ? capacitive load ? ? 50 pf output voltage range 0.35 ? avcc0 - 0.47 v dnl differential non-linearity error ? 0.5 1.0 lsb inl integral non-linearity error ? 2.0 8.0 lsb offset error ? ? 20 mv full-scale error ? ? 20 mv output resistance ? 5 ? ? conversion time ? ? 30 s table 5.52 d/a conversion characteristics (2) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl = vss_usb = 0 v, t a = ?40 to +105c reference voltage = av cc0 or avss0 selected item min. typ. max. unit test conditions resolution ? ? 12 bit resistive load 30 ? ? k ? capacitive load ? ? 50 pf output voltage range 0.35 ? avcc0 - 0.47 v dnl differential non-linearity error ? 0.5 2.0 lsb inl integral non-linearity error ? 2.0 8.0 lsb offset error ? ? 30 mv full-scale error ? ? 30 mv output resistance ? 5 ? ? conversion time ? ? 30 s table 5.53 d/a conversion characteristics (3) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c reference voltage = internal reference voltage selected item min. typ. max. unit test conditions resolution ? ? 12 bit internal reference voltage (vbgr) 1.36 1.43 1.50 v resistive load 30 ? ? k ? capacitive load ? ? 50 pf output voltage range 0.35 ? vbgr v dnl differential non-linearity error ? 2.0 16.0 lsb inl integral non-linearity error ? 8.0 16.0 lsb offset error ? ? 30 mv output resistance ? 5 ? ? conversion time ? ? 30 s
r01ds0261ej0110 rev.1.10 page 150 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.69 illustration of d/a converter characteristic terms integral non-linearity error (inl) the integral non-linearity error is the maximum deviation betw een the ideal line when the m easured offset and full-scale errors are zeroed, and the actual output code. differential non-lin earity error (dnl) the differential non-linearity error is the difference between 1-lsb width based on the ideal d/a conversion characteristics and the width of the actually output code. offset error an offset error is the difference between a transition point of the ideal first output code and the actual first output code. full-scale error a full-scale error is the difference between a transition point of the id eal last output code and the actual last output code. 000h d/a converter input code fffh output analog voltage upper output limit lower output limit offset error ideal output voltage 1-lsb width for ideal d/a conversion characteristic differential nonlinearity error (dnl) actual d/a conversion characteristic *1 integral nonlinearity error (inl) full-scale error gain error offset error ideal output voltage note 1. ideal d/a conversion output voltage that is adj usted so that offset and full scale errors are zeroed.
r01ds0261ej0110 rev.1.10 page 151 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.7 temperature sensor characteristics 5.8 comparator characteristics table 5.54 temperature sensor characteristics conditions: 2.0 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions relative accuracy DD 1.5 D c 2.4 v or above D 2.0 D below 2.4 v temperature slope DD ?3.65 D mv/c output voltage (25c) DD 1.05 D v vcc = 3.3 v temperature sensor start time t start DD 5 s sampling time D 5 DD s table 5.55 comparator characteristics conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions cvrefb0 to cvrefb3 input reference voltage vref 0 ? vcc - 1.4 v cmpb0 to cmpb3 input voltage vi ?0.3 ? vcc + 0.3 v offset comparator high-speed mode ?? ? 50 mv comparator high-speed mode window function enabled ?? ? 60 mv comparator low-speed mode ?? ? 40 mv comparator output delay time comparator high-speed mode td ? ? 1.2 s vcc = 3 v, input slew rate 50 mv/us comparator high-speed mode window function enabled tdw ? ? 2.0 s comparator low-speed mode td ? ? 5.0 s high-side reference voltage (comparator high-speed mode, window function enabled) vrfh ? 0.76 vcc ? v low-side reference voltage (comparator high-speed mode, window function enabled) vrfl ? 0.24 vcc ? v operation stabilization wait time tcmp 100 ? ? s
r01ds0261ej0110 rev.1.10 page 152 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.70 comparator output delay time in comparator high-speed mode and low-speed mode figure 5.71 comparator output delay time in high-speed mode with window function enabled cmpb cmpob td td cvrefb = 0 v cmpb cmpob tdw tdw internal vrh = vcc * 0.76 cmpb cmpob tdw tdw internal vrh = vcc * 0.24
r01ds0261ej0110 rev.1.10 page 153 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.9 ctsu characteristics 5.10 characteristics of power-on rese t circuit and voltage detection circuit note: these characteristics apply when noise is not superimposed on the power supply. when a setting is made so that the voltage detection level overlaps with that of the voltage detection circ uit (lvd2), it cannot be specified which of lvd1 and lvd2 is us ed for voltage detection. note 1. n in the symbol vdet0_n denotes the value of the ofs1.vdsel[1:0] bits. note 2. n in the symbol vdet1_n denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. note 3. n in the symbol vdet2_n denotes the value of the lvdlvlr.lvd2lvl[1:0] bits. table 5.56 ctsu characteristics conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions external capacitance connected to tscap pin c tscap 91011nf ts pin capacitive load c base ??50pf permissible output high current ? i oh ?? ? 24 ma when the mutual capacitance method is applied table 5.57 characteristics of power-on rese t circuit and voltage detection circuit (1) conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 1.35 1.50 1.65 v figure 5.72, figure 5.73 voltage detection circuit (lvd0)* 1 v det0_0 3.67 3.84 3.97 v figure 5.74 at falling edge vcc v det0_1 2.70 2.82 3.00 v det0_2 2.37 2.51 2.67 v det0_3 1.80 1.90 1.99 voltage detection circuit (lvd1)* 2 v det1_0 4.12 4.29 4.42 v figure 5.75 at falling edge vcc v det1_1 3.98 4.14 4.28 v det1_2 3.86 4.02 4.16 v det1_3 3.68 3.84 3.98 v det1_4 2.99 3.10 3.29 v det1_5 2.89 3.00 3.19 v det1_6 2.79 2.90 3.09 v det1_7 2.68 2.79 2.98 v det1_8 2.57 2.68 2.87 v det1_9 2.47 2.58 2.67 v det1_a 2.37 2.48 2.57 v det1_b 2.10 2.20 2.30 v det1_c 1.86 1.96 2.06 v det1_d 1.80 1.86 1.96 voltage detection circuit (lvd2)* 3 v det2_0 4.08 4.29 4.48 v figure 5.76 at falling edge vcc v det2_1 3.95 4.14 4.35 v det2_2 3.82 4.02 4.22 v det2_3 3.62 3.84 4.02
r01ds0261ej0110 rev.1.10 page 154 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: these characteristics apply when noise is not superimposed on the power supply. when a setting is made so that the voltage detection level overlaps with that of the voltage detection circ uit (lvd1), it cannot be specified which of lvd1 and lvd2 is us ed for voltage detection. note 1. when ofs1.(lvdas, faststup) = 11b. note 2. when ofs1.(lvdas, faststup) 11b. note 3. the minimum vcc down time indicates the time when v cc is below the minimum value of voltage detection levels v por , v det0 , v det1 , and v det2 for the por/lvd. table 5.58 characteristics of power-on rese t circuit and voltage detection circuit (2) conditions: 1.8 v vcc0 = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions wait time after power-on reset cancellation at normal startup* 1 t por D 9.1 D ms figure 5.73 during fast startup time* 2 t por D 1.6 D wait time after voltage monitoring 0 reset cancellation power-on voltage monitoring 0 reset disabled* 1 t lvd0 D 568 D s figure 5.74 power-on voltage monitoring 0 reset enabled* 2 D 100 D wait time after voltage monitoring 1 reset cancellation t lvd1 D 100 D s figure 5.75 wait time after voltage monitoring 2 reset cancellation t lvd2 D 100 D s figure 5.76 response delay time t det DD 350 s figure 5.72 minimum vcc down time* 3 t voff 350 DD s figure 5.72, vcc = 1.0 v or above power-on reset enable time t w(por) 1 DD ms figure 5.73, vcc = below 1.0 v lvd operation stabilization time (after lvd is enabled) td (e-a) DD 300 s figure 5.75, figure 5.76 hysteresis width (power-on rest (por)) v porh D 110 D mv hysteresis width (voltage detection circuit: lvd1 and lvd2) v lvh D 70 D mv when vdet1_0 to vdet1_4 is selected D 60 D when vdet1_5 to vdet1_9 is selected D 50 D when vdet1_a or vdet1_b is selected D 40 D when vdet1_c or vdet1_d is selected D 60 D when lvd2 is selected
r01ds0261ej0110 rev.1.10 page 155 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.72 voltage detection reset timing figure 5.73 power-on reset timing figure 5.74 voltage detection circuit timing (vdet0) internal reset signal (active-low) vcc t voff t por t det v por t det 1.0v v porh internal reset signal (active-low) vcc t por v por 1.0 v t w(por) *1 t det note 1. t w(por) is the time required for a power-on reset to be enabled while the external power vcc is being held below the valid voltage (1.0 v). when turning the vcc on, maintain a voltage below 1.0v for at least 1.0ms. v porh t voff v det0 vcc t det t det internal reset signal (active-low) v lvh t lvd0
r01ds0261ej0110 rev.1.10 page 156 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.75 voltage detection circuit timing (v det1 ) figure 5.76 voltage detection circuit timing (v det2 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0261ej0110 rev.1.10 page 157 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.11 oscillation stop detection timing figure 5.77 oscillation stop detection timing table 5.59 oscillation stop detection timing conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions detection time t dr ? ? 1 ms figure 5.77 t dr main clock ostdsr.ostdf low-speed clock ic lk t dr main clock ostdsr.ostdf ic lk when the main clock is selected when the pll clock is selected pll clock low-speed clock
r01ds0261ej0110 rev.1.10 page 158 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.12 battery backup function characteristics note: the vcc-off period for starting power supply switching indicate s the period in which vcc is below the minimum value of the voltage level for switching to battery backup (v detbatt ). figure 5.78 battery backup function characteristics table 5.60 battery backup function characteristics conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, 1.8 v vbatt 5.5 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage level for switching to battery backup (falling) v detbatt 1.99 2.09 2.19 v figure 5.78 hysteresis width v vbatth ?100?mv vcc-off period for starting power supply switching t voffbatt ? ? 350 s allowable voltage change rising/falli ng gradient dt/dvcc 1.0 ? ? ms/v figure 5.7 level for detection of voltage drop on the vbatt pin (falling) vbtlvdlvl[1:0] = 10b v detbatlvd 2.11 2.20 2.29 v figure 5.78 vbtlvdlvl[1:0] = 11b 1.87 2.00 2.13 v hysteresis width for detection of voltage drop on the vbatt pin v batlvdh ?50?mv vcc vbatt backup power supply area vcc supplied vcc supplied vbatt supplied v detbatt vcc voltage guaranteed range vbatt voltage guaranteed range t voffbatt vcc cannot be raised v vbatth v detbatlvd v batlvdh
r01ds0261ej0110 rev.1.10 page 159 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.13 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 1000), erasing can be performed n times for each block. for instance, when 4-byte programming is performed 256 times for different addresses in a 1-kbyte block and th en the entire block is erased, the reprogram/erase cycle i s counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. characteristic when using the flash memory programmer and the self-programming library provided from renesas electronics . note 3. this result is obtained from reliability testing. note: the time until each operation of the flash memory is start ed after instructions are executed by software is not included. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk must be within 3.5%. table 5.61 rom (flash memory for code storage) characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n pec 1000 ? ? times data hold time after 1000 times of n pec t drp 20* 2, * 3 ? ? year t a = +85c table 5.62 rom (flash memory for code storage) characteristics (2) high-speed operating mode conditions: 2.7 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +105c item symbol fclk = 1 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 8-byte t p8 ? 112 967 ? 52.3 491 s erasure time 2-kbyte t e2k ? 8.75 278 ? 5.50 215 ms 512-kbyte (when block erase command is used) t e512k ? 928 19218 ? 72.0 1679 ms 512-kbyte (when all- block erase command is used) t ea512k ? 923 19013 ? 66.7 1469 ms blank check time 8-byte t bc8 ? ? 55.0 ? ? 16.1 s 2-kbyte t bc2k ? ? 1840 ? ? 136 ms erase operation forced stop time t sed ? ? 18.0 ? ? 10.7 s start-up area switching setting time t sas ? 12.3 566.5 ? 6.2 434 ms access window time t aws ? 12.3 566.5 ? 6.2 434 ms rom mode transition wait time 1 t dis 2.0 ? ? 2.0 ? ? s rom mode transition wait time 2 t ms 5.0 ? ? 5.0 ? ? s
r01ds0261ej0110 rev.1.10 page 160 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics note: the time until each operation of the flash memory is start ed after instructions are executed by software is not included. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk must be within 3.5%. table 5.63 rom (flash memory for code storage) characteristics (3) middle-speed operating mode conditions: 1.8 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +85c item symbol fclk = 1 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 8-byte t p8 ? 152 1367 ? 97.9 936 s erasure time 2-kbyte t e2k ? 8.8 279.7 ? 5.9 221 ms 512-kbyte (when block erase command is used) t e512k ? 928 19221 ? 191 4108 ms 512-kbyte (when all- block erase command is used) t ea512k ? 923 19015 ? 185 3901 ms blank check time 8-byte t bc8 ? ? 85.0 ? ? 50.88 s 2-kbyte t bc2k ? ? 1870 ? ? 402 s erase operation forced stop time t sed ? ? 28.0 ? ? 21.3 s start-up area switching setting time t sas ? 13.0 573.3 ? 7.7 451 ms access window time t aws ? 13.0 573.3 ? 7.7 451 ms rom mode transition wait time 1 t dis 2.0 ? ? 2.0 ? ? s rom mode transition wait time 2 t ms 3.0 ? ? 3.0 ? ? s
r01ds0261ej0110 rev.1.10 page 161 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.14 e2 dataflash characteristics (flash memory for data storage) note 1. the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000 ), erasing can be performed n times for each block. for instance, when 1-byte programming is performed 1000 times for different addresses in a 1-kbyte block and then the entire block is eras ed, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). note 2. characteristic when the flash memory programmer is used and the self-programming libr ary is provided from renesas electronics. note 3. these results are obtai ned from reliability testing. note: the time until each operation of the flash memory is start ed after instructions are executed by software is not included. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk must be within 3.5%. note: the time until each operation of the flash memory is start ed after instructions are executed by software is not included. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk must be within 3.5%. table 5.64 e2 dataflash characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n dpec 100000 1000000 ? times data hold time after 10000 times of n dpec t ddrp 20* 2, * 3 ? ? year t a = +85c after 100000 times of n dpec 5* 2, * 3 ? ? year after 1000000 times of n dpec ?1* 2, * 3 ? year t a = +25c table 5.65 e2 dataflash characteristics (2) : high-speed operating mode conditions: 2.7 v vcc = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +105c item symbol fclk = 1 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 1 byte t dp1 ? 95.0 797 ? 40.8 376 s erasure time 1 kbyte t de1k ? 19.5 498 ? 6.2 230 ms 8 kbyte t de8k ? 119.8 2556 ? 12.9 368 ms blank check time 1 byte t dbc1 ? ? 55.00 ? ? 16.1 s 1 kbyte t dbc1k ? ? 0.72 ? ? 0.50 ms erase operation forced stop time t dsed ? ? 16.0 ? ? 10.7 s dataflash stop recovery time t dstop 5.0 ? ? 5.0 ? ? s table 5.66 e2 dataflash characteristics (3) : middle-speed operating mode conditions: 1.8 v vcc0 = vcc_usb = avcc0 5.5 v, vss = avss0 = vss_usb = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +85c item symbol fclk = 1 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 1 byte t dp1 ? 135 1197 ? 86.5 823 s erasure time 1 kbyte t de1k ? 19.6 501 ? 8.0 265 ms 8 kbyte t de8k ? 120 2558 27.7 669 ms blank check time 1 byte t dbc1 ? ? 85.0 ? ? 50.9 s 1 kbyte t dbc1k ? ? 0.72 ? ? 1.45 ms erase operation forced stop time t dsed ? ? 28.0 ? ? 21.3 s dataflash stop recovery time t dstop 0.72 ? ? 0.72 ? ? s
r01ds0261ej0110 rev.1.10 page 162 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics 5.15 usage notes 5.15.1 connecting vcl capacitor and bypass capacitors this mcu integrates an internal voltage-down circuit, which is used for lowering the power supply voltage in the internal mcu automatically to the optimum level. a 4.7- f capacitor needs to be connected between this internal voltage-down power supply (vcl pin) and the vss pin. figure 5.79 to figure 5.81 shows how to connect external capacitors. place an external capacitor close to the pins. do not apply the power supp ly voltage to the vcl pin. insert a multilayer ceramic capacitor as a bypass capacitor between each pair of the power supply pins. implement a bypass capacitor as closer to the mcu power supply pins as possible. use a recommended value of 0.1 f as the capacitance of the capacitors. for the capacito rs related to crystal oscillation, see section 9, clock generation circuit in the user?s manual: hardware . for the capacitors related to analog modules, also see section 43, 12-bit a/d converter (s12ade) in the user?s manual: hardware . for notes on designing the printed circuit board, see the descriptions of the application note, the hardware design guide (r01an1411ej). the latest version can be down loaded from the renesas electronics website.
r01ds0261ej0110 rev.1.10 page 163 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.79 connecting capacitors (100 pins) note: do not apply the power supply voltage to the vcl pin . use a 4.7-f multilayer ceramic capacitor fo r the vcl pin and place it close to the pin . a recommended value is shown for the capacitance of the bypass capacitors . external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f bypass capacitor 0.1 f bypass capacitor 0.1 f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 avcc0 avss0 vss_usb *1 vcc_usb *1 vss vcc vcl vss vcc rx230 group, rx231 group plqp0100kb-b (100-pin lqfp) (top view) bypass capacitor 0.1 f note 1. as the products of the rx230 group do not have vcc_ usb or vss_usb, a bypass capacitor is not required.
r01ds0261ej0110 rev.1.10 page 164 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.80 connecting capacitors (64 pins) note: do not apply the power supply voltage to the vcl pin . use a 4.7-f multilayer ceramic capacitor fo r the vcl pin and place it close to the pin . a recommended value is shown for the capacitance of the bypass capacitors . external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f bypass capacitor 0.1 f bypass capacitor 0.1 f 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx230 group, rx231 group plqp0064kb-c (64-pin lqfp) (top view) avcc0 avss0 vss vcc vss_usb *1 vcc_usb *1 vcl vss vcc bypass capacitor 0.1 f note 1. as the products of the rx230 group do not have vc c_usb or vss_usb, a bypass capacitor is not required.
r01ds0261ej0110 rev.1.10 page 165 of 177 oct 30, 2015 rx230 group, rx231 group 5. electrical characteristics figure 5.81 connecting capacitors (48 pins) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 rx230 group, rx231 group PLQP0048KB-B (48-pin lqfp) (top view) avcc0 avss0 vss vcc vss_usb *1 vcc_usb *1 vss vcc 18 17 16 15 14 13 note: do not apply the power supply voltage to the vcl pin . use a 4.7-f multilayer ceramic capacitor for the vcl pin and place it close to the pin . a recommended value is shown for the capacitance of the bypass capacitors . bypass capacitor 0.1 f external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f bypass capacitor 0.1 f bypass capacitor 0.1 f vcl note 1. as the products of the rx230 group do not have vcc_usb or vss_usb, a bypass capacitor is not required.
r01ds0261ej0110 rev.1.10 page 166 of 177 oct 30, 2015 rx230 group, rx231 group appendix 1. package dimensions appendix 1. package dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation website. figure a 100 -pin tflga (ptlg0100ka-a) e e a b c d e f g h j k 12345678910 b a s ys index mark index mark (laser mark) x4 v a ws b ws d e z d z e a sab m sab m b 1 b 0.15 1.05 0.08 0.08 reference symbol dimension in millimeters min nom max d e v z d b 1 b 5.5 5.5 0.5 0.5 a 0.5 e w x y z e 0.20 0.250.21 0.29 0.340.29 0.39 p-tflga100-5.5x5.5-0.50 0.1g mass[typ.] 100f0m ptlg0100ka-a renesas code jeita package code previous code
r01ds0261ej0110 rev.1.10 page 167 of 177 oct 30, 2015 rx230 group, rx231 group appendix 1. package dimensions figure b 100 -pin lqfp (plqp0100kb-b)
r01ds0261ej0110 rev.1.10 page 168 of 177 oct 30, 2015 rx230 group, rx231 group appendix 1. package dimensions figure c 64 -pin wflga (pwlg0064ka-a) 64-pin plastic flga (5x5) e w 5.00o 0.10 0.20 y 0.20 0.08 y1 zd 0.75 0.05 x d 5.00 o 0.10 a 0.69 o 0.07 b 0.25o 0.04 p64fc-50-an5 ze 0.75 s b s w s y y1 e 0.50 index mark w sa zd ze a b s a b e xs 8 7 6 5 4 3 2 1 bcdefgh a c d c d detail detail e detail m 60x a b item dimensions (unit:mm) 3.90 3.90 b 0.34o0.03 0.55 0.70o0.03 0.55o0.04 0.70o0.03 0.55o0.04 0.75 0.75 0.55 0.55 r0.17o 0.015 r0.17o0.015 r0.125 o 0.02 r0.125o0.02 r0.275o0.02 r0.35o0.015 0.75 0.55o0.04 0.70o0.03 0.55 0.75 0.55o0.04 0.70o0.03 (land pad) (aperture of solder resist) e e d
r01ds0261ej0110 rev.1.10 page 169 of 177 oct 30, 2015 rx230 group, rx231 group appendix 1. package dimensions figure d 64 -pin hwqfn (pwqn0064kc-a) s y e lp sx ba b m a d e 48 32 33 16 17 1 64 a s b a d e 49 detail of a part exposed die pad jeita package code renesas code previous code mass(typ.)[g] p-hwqfn64-9x9-0.50 pwqn0064kc-a p64k8-50-6b4-5 0.21 16 1 17 32 49 64 index area 2 2 d a lp 0.20 7.50 0.40 9.00 9.00 7.50 reference symbol min nom max dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 9.05 8.95 9.05 8.95 z z d e 33 48
r01ds0261ej0110 rev.1.10 page 170 of 177 oct 30, 2015 rx230 group, rx231 group appendix 1. package dimensions figure e 64 -pin lqfp (plqp0064kb-c)
r01ds0261ej0110 rev.1.10 page 171 of 177 oct 30, 2015 rx230 group, rx231 group appendix 1. package dimensions figure f 48 -pin hwqfn (pwqn0048kb-a) s y e lp sx ba b m a d e 36 24 25 12 13 1 48 a s b a d e 37 detail of a part exposed die pad jeita package code renesas code previous code mass(typ.)[g] p-hwqfn48-7x7-0.50 pwqn0048kb-a 48pjn-a 0.13 12 1 13 24 37 48 index area 2 2 d a lp 0.20 5.50 0.40 7.00 7.00 5.50 reference symbol min nom max dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 7.05 6.95 7.05 6.95 z z d e 25 36 p48k8-50-5b4-7
r01ds0261ej0110 rev.1.10 page 172 of 177 oct 30, 2015 rx230 group, rx231 group appendix 1. package dimensions figure g 48 -pin lqfp (PLQP0048KB-B)
r01ds0261ej0110 rev.1.10 page 173 of 177 oct 30, 2015 rx230 group, rx231 group revision history classifications - items with technical update document number: changes according to the corresponding i ssued technical update - items without technical update documen t number: minor changes that do not re quire technical update to be issued revision history rx230 group, rx231 group datasheet rev. date description classification page summary 1.00 jun 24, 2015 ? first edition, issued 1.10 oct 30, 2015 1. overview 3 table 1.1 outline of specifications (2/4), changed 5 table 1.1 outline of specifications (4/4): sd host interface (sdhia) added 6 table 1.2 comparison of functions for different packages: rx230 group added 3. address space 39 figure 3.1 memory map in each operating mode, changed 4. i/o registers 67 table 4.1 list of i/o registers (a ddress order) (25 / 42), changed tn-rx*-a139a/e 83 table 4.1 list of i/o registers (address order) (41 / 42), changed 5. electrical characteristics 85 table 5.1 absolute maximum ratings, changed tn-rx*-a137a/e 86 table 5.2 recommended operating voltage conditions, changed 87 table 5.3 dc characteristics (1), changed tn-rx*-a137a/e 88 table 5.4 dc characteristics (2), changed 88 table 5.5 dc characteristics (3), changed 89 table 5.7 dc characteristics (5), changed 91 figure 5.1 voltage dependency in high-speed operating mode (reference data), changed 92 figure 5.2 voltage dependency in middle-speed operating mode (reference data), changed 93 figure 5.3 voltage dependency in low-speed operating mode (reference data), changed tn-rx*-a137a/e 94 table 5.8 dc characteristics (6), changed figure 5.4 voltage dependency in software standby mode (reference data), changed 95 figure 5.5 temperature dependency in software standby mode (reference data), changed 96 figure 5.6 temperature dependency of rtc operation with vcc off (reference data), changed table 5.10 dc characteristics (8): conditions changed 97 table 5.11 dc characterist ics (9), changed tn-rx*-a137a/e 99 table 5.16 permissible output currents (1), changed tn-rx*-a137a/e 100 table 5.17 permissible output currents (2), changed 101 table 5.18 output values of voltage (1), changed 101 table 5.19 output values of voltage (2), changed tn-rx*-a137a/e 101 table 5.20 output values of voltage (3), changed tn-rx*-a137a/e 105 figure 5.13 voh/vol and ioh/iol voltage characteristics at ta = 25c when high-drive output is selected (reference data), changed tn-rx*-a137a/e 108 figure 5.18 v ol and i ol voltage characteristics of riic output pin at ta = 25c (reference data) tn-rx*-a137a/e 110 table 5.21 operating frequency va lue (high-speed operating mode) and table 5.22 operating frequency value (middle-speed operating mode), changed tn-rx*-a137a/e 112 table 5.26 clock timing, changed tn-rx*-a137a/e 116 table 5.27 reset timing, changed 131 table 5.41 timing of on-chip pe ripheral modules (4): note changed 132 table 5.43 timing of on-chip peripheral modules (6), changed 138 figure 5.61 ssi transmission/recepti on timing (ssicp.sckp=0), changed tn-rx*-a137a/e 139 figure 5.62 ssi transmission/recepti on timing (ssicp.sckp=1), changed tn-rx*-a137a/e 142 figure 5.66 vrefh0 voltage range vs. avcc0, changed revision history
r01ds0261ej0110 rev.1.10 page 174 of 177 oct 30, 2015 rx230 group, rx231 group revision history 1.10 oct 30, 2015 142 table 5.45 a/d conversion characteristics (1): conditions and voltage range of analog input (max.), changed 143 table 5.46 a/d conversion char acteristics (2): conditions changed 144 table 5.47 a/d conversion char acteristics (3): conditions changed 145 table 5.48 a/d conversion char acteristics (4): conditions changed 146 table 5.49 a/d conversion characteristics (5): conditions changed and absolute accuracy (test conditions) deleted 153 table 5.57 characteristics of power-on reset circuit and voltage detection circuit (1), changed tn-rx*-a137a/e 154 table 5.58 characteristics of power-on reset circuit and voltage detection circuit (2), changed 155 figure 5.73 power-on reset timing and figure 5.74 voltage detection circuit timing (vdet0), changed 159 table 5.62 rom (flash memory for code storage) characteristics (2) high- speed operating mode: note changed 160 table 5.63 rom (flash memory for code storage) characteristics (3) middle-speed operating mode: note changed 161 table 5.65 e2 dataflash characteristics (2): high-speed operating mode, note changed 161 table 5.66 e2 dataflash characterist ics (3): middle-speed operating mode, conditions and note changed 163 figure 5.79 connecting ca pacitors (100 pins), changed 164 figure 5.80 connecting ca pacitors (64 pins), changed 165 figure 5.81 connecting ca pacitors (48 pins), changed appendix 1. package dimensions 167 figure b 100 -pin lqfp (plqp0100kb-b), changed tn-rx*-a137a/e 170 figure e 64 -pin lqfp (plqp0064kb-c), changed tn-rx*-a137a/e 172 figure g 48 -pin lqfp (PLQP0048KB-B), changed tn-rx*-a137a/e rev. date description classification page summary
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device.
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rig hts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have sp ecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibi lity of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactur e, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or other wise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this docu ment or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-own ed subsidiaries. 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